📄 uart.pcf
字号:
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/RAMB16"
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/RAMB16"
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/RAMB16"
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/RAMB16"
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/RAMB16"
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/RAMB16"
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/RAMB16"
PINNAME CLKA;
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/RAMB16"
PINNAME CLKA;
TIMEGRP J_CLK = BEL "i_ila/ila/i_yes_d/u_ila/u_rst/u_halt_xfer/u_tfdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_rst/u_arm_xfer/u_tfdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/idout.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/s0_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_14.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/1/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_14.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/2/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_13.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/3/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_11.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/4/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_11.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/5/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_10.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/6/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_8.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/7/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_8.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/8/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_6.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/9/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_6.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/10/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_4.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/11/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_4.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/12/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_2.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/13/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_2.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/14/si_cfg/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/and_out_0.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/15/si_cfg/i_srl_t2/u_srlc16e"
BEL "i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/8/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/7/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/6/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/5/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/4/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/3/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/2/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/1/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_stat_cnt/g/0/u_fdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl1/u_tfdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dirty" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_reset_edge/u_dout0" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_reset_edge/u_dout1" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_reset_edge/i_h2l/u_dout" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_tdo" BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/0/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/1/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/2/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/3/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/4/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/5/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/6/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/7/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/8/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/9/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/10/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/11/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/12/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/13/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/14/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/15/u_sel"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/i_srl/u_selx"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxl/O.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxl/O.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxl/O.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxl/O.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxl/O.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxl/O.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug3_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_0.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf3_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_0.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug2_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_1.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf2_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_1.SLICEM_FMC15_BLACKBOX"
BEL
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