📄 uart.pcf
字号:
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
BEL "i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_cap_dly" BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/1/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/2/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/3/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/4/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/5/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/6/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/7/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/8/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/9/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/10/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/11/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/12/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/13/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/14/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/u_states/15/u_srl/u_fdr0"
BEL
"i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_tseq_simple/final_fdr"
BEL "i_ila/ila/i_yes_d/u_ila/u_trig/f_no_tcmc/u_fdr" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl1/u_dout0" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl1/u_dout1" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl1/u_dout" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl1/u_rfdre" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl1/u_gen_delay/1/u_fd" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl2" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_dsl3" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_cr" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/11/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/10/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/9/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/8/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/7/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/6/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/5/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/4/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/3/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/2/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/1/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/g_ns/0/u_nsq" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_state1" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_state0" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_arm" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_trigger" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_full" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_tsof" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_ecr" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_ece" BEL
"i_ila/ila/i_yes_d/u_ila/u_stat/u_rising" BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_icap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_cap_addr"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/11/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/10/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/9/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/8/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/7/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/6/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/5/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/4/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/3/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/2/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/1/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/0/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/11/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/10/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/9/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/8/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/7/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/6/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/5/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/4/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/3/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/2/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/1/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/0/u_fdre"
BEL "i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_hcmp_q" BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_lcmp_q" BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_scnt_cmp_q" BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
BEL "i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe0"
BEL "i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe1"
BEL "i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig0" BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig1" BEL "rxdata_7" BEL
"rxdata_6" BEL "rxdata_5" BEL "rxdata_4" BEL "rxdata_3" BEL "hunt" BEL
"rxdata_2" BEL "rxdata_1" BEL "data1_5" BEL "data1_4" BEL "data1_3"
BEL "data1_6" BEL "data1_1" BEL "data1_2" BEL "data1_0" BEL "cnt2_25"
BEL "cnt2_0" BEL "cnt2_1" BEL "cnt2_2" BEL "cnt2_3" BEL "cnt2_4" BEL
"cnt2_5" BEL "cnt2_6" BEL "cnt2_7" BEL "cnt2_8" BEL "cnt2_9" BEL
"cnt2_10" BEL "cnt2_11" BEL "cnt2_12" BEL "cnt2_13" BEL "cnt2_14" BEL
"cnt2_15" BEL "cnt2_16" BEL "cnt2_17" BEL "cnt2_18" BEL "cnt2_19" BEL
"cnt2_20" BEL "cnt2_21" BEL "cnt2_22" BEL "cnt2_23" BEL "cnt1_27" BEL
"cnt1_29" BEL "cnt1_28" BEL "cnt1_0" BEL "cnt1_1" BEL "cnt1_2" BEL
"cnt1_3" BEL "cnt1_4" BEL "cnt1_5" BEL "cnt1_6" BEL "cnt1_7" BEL
"cnt1_8" BEL "cnt1_9" BEL "cnt1_10" BEL "cnt1_11" BEL "cnt1_12" BEL
"cnt1_13" BEL "cnt1_14" BEL "cnt1_15" BEL "cnt1_16" BEL "cnt1_17" BEL
"cnt1_18" BEL "cnt1_19" BEL "cnt1_20" BEL "cnt1_21" BEL "cnt1_22" BEL
"cnt1_23" BEL "cnt1_24" BEL "cnt1_25" BEL "u1/cnt2_24" BEL "u1/busy"
BEL "u1/data_out" BEL "u1/cnt1_28" BEL "u1/cnt2_25" BEL "u1/cnt2_0"
BEL "u1/cnt2_1" BEL "u1/cnt2_2" BEL "u1/cnt2_3" BEL "u1/cnt2_4" BEL
"u1/cnt2_5" BEL "u1/cnt2_6" BEL "u1/cnt2_7" BEL "u1/cnt2_8" BEL
"u1/cnt2_9" BEL "u1/cnt2_10" BEL "u1/cnt2_11" BEL "u1/cnt2_12" BEL
"u1/cnt2_13" BEL "u1/cnt2_14" BEL "u1/cnt2_15" BEL "u1/cnt2_16" BEL
"u1/cnt2_17" BEL "u1/cnt2_18" BEL "u1/cnt2_19" BEL "u1/cnt2_20" BEL
"u1/cnt2_21" BEL "u1/cnt2_22" BEL "u1/cnt2_23" BEL "u1/cnt1_29" BEL
"u1/cnt1_0" BEL "u1/cnt1_1" BEL "u1/cnt1_2" BEL "u1/cnt1_3" BEL
"u1/cnt1_4" BEL "u1/cnt1_5" BEL "u1/cnt1_6" BEL "u1/cnt1_7" BEL
"u1/cnt1_8" BEL "u1/cnt1_9" BEL "u1/cnt1_10" BEL "u1/cnt1_11" BEL
"u1/cnt1_12" BEL "u1/cnt1_13" BEL "u1/cnt1_14" BEL "u1/cnt1_15" BEL
"u1/cnt1_16" BEL "u1/cnt1_17" BEL "u1/cnt1_18" BEL "u1/cnt1_19" BEL
"u1/cnt1_20" BEL "u1/cnt1_21" BEL "u1/cnt1_22" BEL "u1/cnt1_23" BEL
"u1/cnt1_24" BEL "u1/cnt1_25" BEL "u1/cnt1_26" BEL "u1/cnt1_27" BEL
"u1/cnt_3" BEL "u1/cnt_0" BEL "u1/cnt_1" BEL "u1/cnt_2" PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/RAMB16_pins<158>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/RAMB16_pins<158>";
PIN
i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/RAMB16_pins<159>
= BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/RAMB16"
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