uart.mrp

用Verilog实现的串口异步通信

The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/DOB<0>" is sourceless and has been
removed.
The signal "i_icon/u_icon/icommand_sel_12" is sourceless and has been removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/3/u_lce" (ROM)
removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/3/u_hce" (ROM)
removed.
The signal "i_icon/u_icon/icommand_sel_9" is sourceless and has been removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/6/u_lce" (ROM)
removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/6/u_hce" (ROM)
removed.
The signal "i_icon/u_icon/icommand_sel_8" is sourceless and has been removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/7/u_lce" (ROM)
removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/7/u_hce" (ROM)
removed.
The signal "i_icon/u_icon/icommand_sel_4" is sourceless and has been removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/11/u_lce" (ROM)
removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/11/u_hce" (ROM)
removed.
The signal "i_icon/u_icon/icommand_sel_3" is sourceless and has been removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/12/u_lce" (ROM)
removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/12/u_hce" (ROM)
removed.
The signal "i_icon/u_icon/icommand_sel_2" is sourceless and has been removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/13/u_lce" (ROM)
removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/13/u_hce" (ROM)
removed.
The signal "i_icon/u_icon/icommand_sel_1" is sourceless and has been removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/14/u_lce" (ROM)
removed.
 Sourceless block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/14/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/11/u_lut" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/12/u_lut" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/13/u_lut" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/14/u_lut" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/3/u_lut" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/6/u_lut" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/7/u_lut" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/1/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/10/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/15/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/2/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/4/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/5/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/8/u_hce" (ROM)
removed.
Unused block "i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/9/u_hce" (ROM)
removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
GND 		i_icon/GND
VCC 		i_icon/VCC
LUT4 		i_icon/icon/u_icon/u_stat/f_stat/3/u_stat
LUT3 		i_icon/icon/u_icon/u_tdo_mux/i4/fj/1/u_lut3
LUT3 		i_icon/icon/u_icon/u_tdo_mux/i4/fj/2/u_lut3
LUT3 		i_icon/icon/u_icon/u_tdo_mux/i4/fj/3/u_lut3
LUT3 		i_icon/icon/u_icon/u_tdo_mux/i4/fj/4/u_lut3
LUT3 		i_icon/icon/u_icon/u_tdo_mux/i4/fj/5/u_lut3
LUT3 		i_icon/icon/u_icon/u_tdo_mux/i4/fj/6/u_lut3
GND 		i_ila/GND
VCC 		i_ila/VCC
LUT4 		i_ila/ila/i_yes_d/u_ila/u_stat/f_sstat/7/i_stat/u_stat
LUT4 		i_ila/ila/i_yes_d/u_ila/u_stat/f_sstat/8/i_stat/u_stat
LUT4 		i_ila/ila/i_yes_d/u_ila/u_stat/f_sstat/9/i_stat/u_stat
LUT3 		i_ila/ila/i_yes_d/u_ila/u_stat/u_smux/i5/fj/10/u_lut3
LUT3 		i_ila/ila/i_yes_d/u_ila/u_stat/u_smux/i5/fj/11/u_lut3
LUT3 		i_ila/ila/i_yes_d/u_ila/u_stat/u_smux/i5/fj/12/u_lut3
LUT3 		i_ila/ila/i_yes_d/u_ila/u_stat/u_smux/i5/fj/13/u_lut3
LUT3 		i_ila/ila/i_yes_d/u_ila/u_stat/u_smux/i5/fj/14/u_lut3
LUT3 		i_ila/ila/i_yes_d/u_ila/u_stat/u_smux/i5/fj/15/u_lut3
LUT3 		i_ila/ila/i_yes_d/u_ila/u_stat/u_smux/i5/fj/7/u_lut3

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |             | Strength | Rate |              |          | Delay    |
+----------------------------------------------------------------------------------------------------------------------------------------+
| CLK                                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| data1<0>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data1<1>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data1<2>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data1<3>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data1<4>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data1<5>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data1<6>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data1<7>                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| data_in                            | IOB              | INPUT     | LVCMOS25    |          |      | IFF1         |          |          |
| data_out                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
+----------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------
i_ila/ila/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm
i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
--------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 11
Number of Equivalent Gates for Design = 13,113
Number of RPM Macros = 12
Number of Hard Macros = 0
PMV = 0
USR_ACCESS_VIRTEX4 = 0
BUFIO = 0
GT11CLK = 0
GT11 = 0
IDELAYCTRL = 0
FRAME_ECC_VIRTEX4 = 0
STARTUP_VIRTEX4 = 0
JTAGPPC = 0
ICAP_VIRTEX4 = 0
DPM = 0
DCI_TEST = 0
DCIRESET = 0
CAPTURE_VIRTEX4 = 0
BSCAN_VIRTEX4 = 1
OSERDES = 0
ISERDES = 0
BUFR = 0
EMAC = 0
PPC405_ADV = 0
MONITOR = 0
PMCD = 0
DCM_ADV = 0
DSP48 = 0
Unbonded IOBs = 0
Bonded IOBs = 11
XORs = 168
CARRY_INITs = 95
CARRY_SKIPs = 0
CARRY_MUXes = 170
Shift Registers = 101
Static Shift Registers = 37
Dynamic Shift Registers = 64
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFs = 78
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 87
4 input LUTs = 335
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 210
Slice Flip Flops = 424
SliceMs = 65
SliceLs = 386
Slices = 451
F6 Muxes = 20
F5 Muxes = 53
F8 Muxes = 1
F7 Muxes = 4
Xilinx Core null = 2
Number of LUT signals with 4 loads = 10
Number of LUT signals with 3 loads = 13
Number of LUT signals with 2 loads = 7
Number of LUT signals with 1 load = 278
NGM Average fanout of LUT = 2.29
NGM Maximum fanout of LUT = 77
NGM Average fanin for LUT = 3.3164
Number of LUT symbols = 335