uart.mrp

用Verilog实现的串口异步通信

Release 7.1.04i Map H.42
Xilinx Mapping Report File for Design 'uart'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -ise d:\found.000\uart\uart.ise
-intstyle ise -p xc4vsx35-ff668-10 -cm area -pr b -k 4 -c 100 -o uart_map.ncd
uart.ngd uart.pcf 
Target Device  : xc4vsx35
Target Package : ff668
Target Speed   : -10
Mapper Version : virtex4 -- $Revision: 1.26.6.4 $
Mapped Date    : Sat Jan 12 16:38:56 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         424 out of  30,720    1%
  Number of 4 input LUTs:             335 out of  30,720    1%
Logic Distribution:
  Number of occupied Slices:                          451 out of  15,360    2%
    Number of Slices containing only related logic:     451 out of     451  100%
    Number of Slices containing unrelated logic:          0 out of     451    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            523 out of  30,720    1%
  Number used as logic:                335
  Number used as a route-thru:          87
  Number used as Shift registers:      101
  Number of bonded IOBs:               11 out of     448    2%
  Number of BUFG/BUFGCTRLs:             2 out of      32    6%
    Number used as BUFGs:                2
    Number used as BUFGCTRLs:            0
  Number of FIFO16/RAMB16s:             9 out of     192    4%
    Number used as FIFO16s:              0
    Number used as RAMB16s:              9
  Number of BSCAN_VIRTEX4s:             1 out of       4   25%

   Number of RPM macros:           12
Total equivalent gate count for design:  13,113
Additional JTAG gate count for IOBs:  528
Peak Memory Usage:  204 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network control0<7> has no load.
WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 57
   more times for the following (max. 5 shown):
   control0<15>,
   control0<10>,
   control0<16>,
   control0<11>,
   control0<17>
   To see the details of these warning messages, please use the -detail switch.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:742 - Your design is targeting LX/SX Production Step 0/1/ES devices.
   Please note that there are new specifications for the DCMs to guarantee
   maximum frequency performance. If the DCM input clock might stop or if the
   DCM reset might be asserted for an extended time, then use of the dcm_standby
   macro may be required. Please see Answer Record 21127.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
  45 block(s) removed
  64 block(s) optimized away
  65 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/1/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/10/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/11/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/12/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/13/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/14/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/2/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/3/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/4/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/5/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/6/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/7/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/8/u_lut" (ROM)
removed.
Loadless block "i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/9/u_lut" (ROM)
removed.
Loadless block "i_ila/ila/i_yes_d/u_ila/u_stat/u_dsr" (ROM) removed.
Loadless block "i_ila/ila/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_cap_b"
(ROM) removed.
The signal "control0<7>" is sourceless and has been removed.
The signal "control0<15>" is sourceless and has been removed.
The signal "control0<10>" is sourceless and has been removed.
The signal "control0<16>" is sourceless and has been removed.
The signal "control0<11>" is sourceless and has been removed.
The signal "control0<17>" is sourceless and has been removed.
The signal "control0<18>" is sourceless and has been removed.
The signal "control0<30>" is sourceless and has been removed.
The signal "control0<24>" is sourceless and has been removed.
The signal "control0<31>" is sourceless and has been removed.
The signal "control0<25>" is sourceless and has been removed.
The signal "control0<32>" is sourceless and has been removed.
The signal "control0<26>" is sourceless and has been removed.
The signal "control0<21>" is sourceless and has been removed.
The signal "control0<33>" is sourceless and has been removed.
The signal "control0<28>" is sourceless and has been removed.
The signal "control0<27>" is sourceless and has been removed.
The signal "control0<22>" is sourceless and has been removed.
The signal "control0<34>" is sourceless and has been removed.
The signal "control0<29>" is sourceless and has been removed.
The signal "control0<23>" is sourceless and has been removed.
The signal "control0<35>" is sourceless and has been removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/DOB<1>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/DOB<0>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/DOB<3>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/DOB<2>" is sourceless and has been
removed.
The signal
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/
ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/DOB<1>" is sourceless and has been
removed.