uart.bld

用Verilog实现的串口异步通信

Release 7.1.04i ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd d:\found.000\uart/_ngo -nt timestamp
-uc uart_constraints.ucf -p xc4vsx35-ff668-10 uart.ngc uart.ngd 

Reading NGO file 'D:/FOUND.000/uart/uart.ngc' ...
Reading module "ila.ngo" ( "ila.ngo" unchanged since last run )...
Loading design module "d:\found.000\uart\_ngo\ila.ngo"...
Reading module "icon.ngo" ( "icon.ngo" unchanged since last run )...
Loading design module "d:\found.000\uart\_ngo\icon.ngo"...

Applying constraints in "uart_constraints.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 80224 kilobytes

Writing NGD file "uart.ngd" ...

Writing NGDBUILD log file "uart.bld"...