uart.syr

用Verilog实现的串口异步通信

Optimizing unit <send> ...
Loading device for application Rf_Device from file '4vsx35.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u1/data_out_flag> is unconnected in block <uart>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : uart.ngr
Top Level Output File Name         : uart
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 11

Macro Statistics :
# Registers                        : 23
#      1-bit register              : 17
#      26-bit register             : 5
#      8-bit register              : 1
# Multiplexers                     : 1
#      1-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 5
#      26-bit adder                : 5

Cell Usage :
# BELS                             : 531
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 12
#      LUT1_L                      : 96
#      LUT2                        : 6
#      LUT2_D                      : 1
#      LUT2_L                      : 4
#      LUT3                        : 4
#      LUT3_D                      : 5
#      LUT3_L                      : 7
#      LUT4                        : 37
#      LUT4_D                      : 8
#      LUT4_L                      : 121
#      MUXCY                       : 108
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 108
# FlipFlops/Latches                : 140
#      FD                          : 120
#      FDE                         : 19
#      FDR                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 10
#      IBUF                        : 1
#      OBUF                        : 9
# Others                           : 2
#      icon                        : 1
#      ila                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-10 

 Number of Slices:                     165  out of  15360     1%  
 Number of Slice Flip Flops:           140  out of  30720     0%  
 Number of 4 input LUTs:               301  out of  30720     0%  
 Number of bonded IOBs:                 11  out of    450     2%  
 Number of GCLKs:                        1  out of     32     3%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 140   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -10

   Minimum period: 5.464ns (Maximum Frequency: 182.999MHz)
   Minimum input arrival time before clock: 3.689ns
   Maximum output required time after clock: 4.869ns
   Maximum combinational path delay: 1.643ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 5.464ns (frequency: 182.999MHz)
  Total number of paths / destination ports: 7725 / 158
-------------------------------------------------------------------------
Delay:               5.464ns (Levels of Logic = 5)
  Source:            cnt1_7 (FF)
  Destination:       cnt1_9 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: cnt1_7 to cnt1_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.360   0.781  cnt1_7 (cnt1_7)
     LUT4:I0->O            1   0.195   0.547  _n000342 (CHOICE987)
     LUT4:I3->O            3   0.195   0.728  _n000346 (CHOICE988)
     LUT4:I1->O            4   0.195   0.624  _n0003154_1 (_n0003154)
     LUT3_D:I2->O         13   0.195   0.728  flag11 (N656)
     MUXF5:S->O            1   0.527   0.000  cnt1_142 (N668)
     FD:D                      0.391          cnt1_14
    ----------------------------------------
    Total                      5.464ns (2.058ns logic, 3.406ns route)
                                       (37.7% logic, 62.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              3.689ns (Levels of Logic = 2)
  Source:            data_in (PAD)
  Destination:       hunt (FF)
  Destination Clock: CLK rising

  Data Path: data_in to hunt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.965   0.730  data_in_IBUF (data_in_IBUF)
     LUT2:I1->O            1   0.195   0.534  _n00481 (_n0048)
     FDR:R                     1.265          hunt
    ----------------------------------------
    Total                      3.689ns (2.425ns logic, 1.264ns route)
                                       (65.7% logic, 34.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 19 / 19
-------------------------------------------------------------------------
Offset:              4.869ns (Levels of Logic = 1)
  Source:            u1/data_out (FF)
  Destination:       data_out (PAD)
  Source Clock:      CLK rising

  Data Path: u1/data_out to data_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.360   0.552  u1/data_out (u1/data_out)
     OBUF:I->O                 3.957          data_out_OBUF (data_out)
    ----------------------------------------
    Total                      4.869ns (4.317ns logic, 0.552ns route)
                                       (88.7% logic, 11.3% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 37 / 37
-------------------------------------------------------------------------
Delay:               1.643ns (Levels of Logic = 1)
  Source:            CLK (PAD)
  Destination:       i_ila:clk (PAD)

  Data Path: CLK to i_ila:clk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O          140   0.000   1.643  CLK_BUFGP (CLK_BUFGP)
    ila:clk                    0.000          i_ila
    ----------------------------------------
    Total                      1.643ns (0.000ns logic, 1.643ns route)
                                       (0.0% logic, 100.0% route)

=========================================================================
CPU : 17.22 / 17.69 s | Elapsed : 17.00 / 17.00 s
 
--> 

Total memory usage is 215000 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    0 (   0 filtered)