uart.syr

用Verilog实现的串口异步通信

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: uart.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "uart.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "uart"
Output Format                      : NGC
Target Device                      : xc4vsx35-10-ff668

---- Source Options
Top Module Name                    : uart
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Number of Regional Clock Buffers   : Default
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : uart.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
use_dsp48                          : auto
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Auto
use_sync_set                       : Auto
use_sync_reset                     : Auto
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "send.v"
Module <send> compiled
Compiling verilog file "icon_xst_example.v"
Module <icon_xst_example> compiled
Module <icon> compiled
Compiling verilog file "ila_xst_example.v"
Module <ila_xst_example> compiled
Module <ila> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
No errors in compilation
Analysis of file <"uart.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <uart>.
Module <uart> is correct for synthesis.
 
Analyzing module <send>.
Module <send> is correct for synthesis.
 
Analyzing module <icon>.
Generating a Black Box for module <icon>.
 
Analyzing module <ila>.
Generating a Black Box for module <ila>.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <send>.
    Related source file is "send.v".
    Found 1-bit register for signal <data_out>.
    Found 1-bit register for signal <data_out_flag>.
    Found 1-bit register for signal <busy>.
    Found 4-bit up counter for signal <cnt>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Summary:
	inferred   3 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <send> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 8-bit register for signal <data1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0001>.
    Found 1-bit register for signal <busy>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Found 1-bit register for signal <flag>.
    Found 1-bit register for signal <hunt>.
    Found 1-bit register for signal <hunt1>.
    Found 10-bit register for signal <rxdata>.
    Summary:
	inferred   2 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <uart> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 26-bit up counter                 : 2
 30-bit up counter                 : 2
 4-bit up counter                  : 1
# Registers                        : 18
 1-bit register                    : 17
 8-bit register                    : 1
# Multiplexers                     : 1
 1-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Reading module "ila.ngo" ( "ila.ngo" unchanged since last run )...
Reading module "icon.ngo" ( "icon.ngo" unchanged since last run )...
WARNING:Xst:1474 - Core <ila> was not loaded for <i_ila> as one or more ports did not line up with component declaration.  Declared input port <control<35>> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.
WARNING:Xst:1474 - Core <icon> was not loaded for <i_icon> as one or more ports did not line up with component declaration.  Declared output port <control0<3>> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.
WARNING:Xst:1291 - FF/Latch <data_out_flag> is unconnected in block <u1>.

Optimizing unit <uart> ...