send.v

用Verilog实现的串口异步通信

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:09:24 01/11/08
// Design Name:    
// Module Name:    send
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module send(CLK,flag,data_in,data_out,data_out_flag);
 input CLK;
 input [7:0]data_in;
 output reg data_out;
 output reg data_out_flag;
 input flag;
 reg busy=0;
 reg [29:0]cnt1=0;
 reg [25:0]cnt2=0;
 reg [3:0]cnt;

 always@(posedge CLK) begin
  if(flag) begin
   busy<=1;								 //FPGA收到帧后准备开始发帧
  end

  if(busy) begin
   cnt1<=cnt1+1;
	cnt2<=cnt2+1;
  end

  if(cnt2==3413-1) begin			 //在第二百个采样点处引入输出数据
   cnt2<=0;
  end

  if(cnt1==34133-1-2500) begin
   busy<=0;
	cnt1<=0;
	cnt2<=0;
  end

 end

 always@(posedge CLK) begin
  if(busy==1&&cnt2==200) begin
   data_out_flag<=1;
   if(cnt==9) begin						 //在第二百个采样点处串行输出数据
	 cnt<=0;
	end
	else begin
	 cnt<=cnt+1;
	end

	case(cnt)
	 4'b0000:data_out<=0;
	 4'b0001:data_out<=data_in[7];
	 4'b0010:data_out<=data_in[6];
	 4'b0011:data_out<=data_in[5];
	 4'b0100:data_out<=data_in[4];
	 4'b0101:data_out<=data_in[3];
	 4'b0110:data_out<=data_in[2];
	 4'b0111:data_out<=data_in[1];
	 4'b1000:data_out<=data_in[0];
	 4'b1001:data_out<=1;
	endcase

  end
  else begin
   data_out_flag<=0;
  end
 end

endmodule