uart.twr

用Verilog实现的串口异步通信

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise d:\found.000\uart\uart.ise -intstyle ise -e 3 -l
3 -s 10 -xml uart uart.ncd -o uart.twr uart.pcf


Design file:              uart.ncd
Physical constraint file: uart.pcf
Device,speed:             xc4vsx35,-10 (PRODUCTION 1.57 2005-08-24, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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WARNING:Timing:2666 - Constraint ignored: PATH "TS_U_TO_D_path" TIG;
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" TO TIMEGRP "J_CLK" 30 ns;

 2567 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   7.117ns.
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================================================================================
Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns;

 18 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.426ns.
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================================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;

 1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   0.968ns.
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================================================================================
Timing constraint: PATH "TS_U_TO_D_path" TIG;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: PATH "TS_J_TO_D_path" TIG;

 155 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
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================================================================================
Timing constraint: PATH "TS_D_TO_J_path" TIG;

 251 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
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All constraints were met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 2992 paths, 0 nets, and 1114 connections

Design statistics:
   Minimum period:   7.117ns (Maximum frequency: 140.509MHz)
   Maximum path delay from/to any node:   7.117ns


Analysis completed Sat Jan 12 16:40:27 2008
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Peak Memory Usage: 188 MB