yibutongxin.syr

用VHDL编写的串口异步通信的例子

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: yibutongxin.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "yibutongxin.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "yibutongxin"
Output Format                      : NGC
Target Device                      : acr2

---- Source Options
Top Module Name                    : yibutongxin
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : yibutongxin.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/program files/Xilinx ISE 7.1i/New Folder/yibutongxin/yibutongxin.vhd" in Library work.
Architecture behavioral of Entity yibutongxin is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <yibutongxin> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - "E:/program files/Xilinx ISE 7.1i/New Folder/yibutongxin/yibutongxin.vhd" line 35: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/program files/Xilinx ISE 7.1i/New Folder/yibutongxin/yibutongxin.vhd" line 36: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/program files/Xilinx ISE 7.1i/New Folder/yibutongxin/yibutongxin.vhd" line 39: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/program files/Xilinx ISE 7.1i/New Folder/yibutongxin/yibutongxin.vhd" line 40: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <yibutongxin> analyzed. Unit <yibutongxin> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <yibutongxin>.
    Related source file is "E:/program files/Xilinx ISE 7.1i/New Folder/yibutongxin/yibutongxin.vhd".
WARNING:Xst:646 - Signal <intran> is assigned but never used.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 16                                             |
    | Transitions        | 21                                             |
    | Inputs             | 2                                              |
    | Outputs            | 17                                             |
    | Clock              | rxclk (rising_edge)                            |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <ldsr>.
    Found 1-bit register for signal <ldrb>.
    Found 1-bit register for signal <fe>.
    Found 8-bit register for signal <d>.
    Found 8-bit register for signal <rxbuff>.
    Found 1-bit register for signal <sclk>.
    Found 9-bit register for signal <data1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  13 D-type flip-flop(s).
Unit <yibutongxin> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 19
 1-bit register                    : 17
 8-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Optimizing FSM <FSM_0> on signal <state[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 s0    | 0000
 s1    | 0001
 s2    | 0010
 s3    | 0011
 s4    | 0100
 s5    | 0101
 s6    | 0110
 s7    | 0111
 s8    | 1000
 s9    | 1001
 s10   | 1010
 s11   | 1011
 s12   | 1101
 s13   | 1100
 s14   | 1110
 s15   | 1111
-------------------

Optimizing unit <yibutongxin> ...
  implementation constraint: INIT=r	 : state_FFd1
  implementation constraint: INIT=r	 : state_FFd2
  implementation constraint: INIT=r	 : state_FFd3
  implementation constraint: INIT=r	 : state_FFd4

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : yibutongxin.ngr
Top Level Output File Name         : yibutongxin
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : acr2
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 24

Macro Statistics :
# Registers                        : 29
#      1-bit register              : 29

Cell Usage :
# BELS                             : 166
#      AND2                        : 51
#      AND3                        : 6
#      AND4                        : 5
#      GND                         : 1
#      INV                         : 83
#      OR2                         : 18
#      XOR2                        : 2
# FlipFlops/Latches                : 33
#      FD                          : 16
#      FDCE                        : 17
# IO Buffers                       : 24
#      IBUF                        : 4
#      OBUF                        : 20
=========================================================================
CPU : 16.95 / 20.17 s | Elapsed : 17.00 / 19.00 s
 
--> 

Total memory usage is 81032 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    4 (   0 filtered)