yibutongxin.vhd

用VHDL编写的串口异步通信的例子

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-- Company: 
-- Engineer:
--
-- Create Date:    19:38:56 03/26/07
-- Design Name:    
-- Module Name:    yibutongxin - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity yibutongxin is
  port(sin:in std_logic; --串行输入端口
rxclk:in std_logic; --接收时钟
txclk:in std_logic; --发送时钟
tran:in std_logic; --要求发送信号
ldsr:buffer std_logic; --接收移位寄存器置初值信号
ldrb:buffer std_logic; --接收缓存装入信号
fe:out std_logic; --祯错误信号
d:out std_logic_vector(7 downto 0); --并行输出端口
rxbuff:buffer std_logic_vector(7 downto 0); --接收缓存
sclk:buffer std_logic  --采样时钟
); 

end yibutongxin;

architecture Behavioral of yibutongxin is

type s is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);--枚举16个状态
signal state:s; --定义接收状态机及其信号
signal data1:std_logic_vector(9 downto 1); --9位移位寄存器
signal intran:std_logic; --内部要求发送信号
signal flag:std_logic; --用于同步发送信号的标志信号

begin

receive:process(rxclk)
begin
if rxclk'event and rxclk='1' then
case state is
 when s0=> ldsr<='0';ldrb<='0';fe<='0';sclk<='0';	 
   if sin='0' then
    state<=s1;
   else state<=s0;
   end if;
 when s1=> state<=s2;
 when s2=> ldsr<='1';state<=s3;
 when s3=> ldsr<='0';state<=s4;
 when s4=> 
   if sin='0' then
    sclk<='1';state<=s5;
   else state<=s0;
   end if;
 when s5=> sclk<='0';state<=s6;
 when s6=> state<=s7;
 when s7=> state<=s8;
 when s8=> state<=s9;
 when s9=> state<=s10;
 when s10=> state<=s11;
 when s11=> 
  if data1(9)='0' then
   state<=s13;
  else state<=s12;
  end if;
 when s12=> sclk<='1';state<=s5;
 when s13=> 
  if sin='1' then
   state<=s14;
  else state<=s15;
  end if;
 when s14=> ldrb<='1';state<=s0;
 when s15=> fe<='1';
  if sin='1' then
   state<=s14;
  else state<=s15;
  end if;
end case;
end if;
end process receive;

Reg:process(rxclk)

begin

if rxclk'event and rxclk='0' then
 if ldsr='1' then
  data1<="111111111";
 end if;
 if state=s0 then
  data1<="111111111";
 end if;
 if sclk='1' then
  data1(9 downto 2)<=data1(8 downto 1);
  data1(1)<=sin;
 end if;
end if;
end process Reg;

crbuff:process(rxclk)

begin

if rxclk'event and rxclk='0' then
 if state=s0 then
  rxbuff<="00000000";
 end if;
 if ldrb='1' then
  rxbuff<=data1(8 downto 1);
 else rxbuff<=rxbuff;
 end if;
end if;
end process crbuff;

pacestran:process(txclk,tran)

begin

if tran='1' then
 intran<='1';
else 
 if txclk'event and txclk='1' then
  if flag='0' then
   intran<='0';
  else intran<='1';
  end if;
 end if;
end if;
end process pacestran;

stran:process(txclk)

begin

if txclk'event and txclk='0' then
 if tran='0' then
  d<=rxbuff;
  flag<='1';
 else flag<='0';d<="00000000";
 end if;
end if;
end process stran;


end Behavioral;