kk.vhd

用VHDL编写的串口异步通信的例子

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-- Company: 
-- Engineer:
--
-- Create Date:   21:57:26 03/26/2007
-- Design Name:   yibutongxin
-- Module Name:   kk.vhd
-- Project Name:  yibutongxin
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: yibutongxin
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY kk_vhd IS
END kk_vhd;

ARCHITECTURE behavior OF kk_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT yibutongxin
	PORT(
		sin : IN std_logic;
		rxclk : IN std_logic;
		txclk : IN std_logic;
		tran : IN std_logic;          
		ldsr : OUT std_logic;
		ldrb : OUT std_logic;
		fe : OUT std_logic;
		d : OUT std_logic_vector(7 downto 0);
		rxbuff : OUT std_logic_vector(7 downto 0);
		sclk : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL sin :  std_logic := '0';
	SIGNAL rxclk :  std_logic := '0';
	SIGNAL txclk :  std_logic := '0';
	SIGNAL tran :  std_logic := '0';

	--Outputs
	SIGNAL ldsr :  std_logic;
	SIGNAL ldrb :  std_logic;
	SIGNAL fe :  std_logic;
	SIGNAL d :  std_logic_vector(7 downto 0);
	SIGNAL rxbuff :  std_logic_vector(7 downto 0);
	SIGNAL sclk :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: yibutongxin PORT MAP(
		sin => sin=“11110000”,
		rxclk => rxclk,
		txclk => txclk,
		tran => tran=0,
		ldsr => ldsr=1,
		ldrb => ldrb=1,
		fe => fe,
		d => d,
		rxbuff => rxbuff,
		sclk => sclk
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;