yibutongxin.xml

用VHDL编写的串口异步通信的例子

<document><ascFile>yibutongxin.rpt</ascFile><devFile>D:/Program Files/Xilinx ISE 7.1i/acr2/data/xa2c32a.chp</devFile><mfdFile>yibutongxin.mfd</mfdFile><htmlFile logo="coolrunnerII_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="VQ44" date=" 3-27-2007" time=" 11:46AM" speed="-6" design="yibutongxin" device="XA2C32A" status="10" eqnType="1" version="1.0" statusStr="Design Rule Checking Failed" swVersion="H.42"/><inputs id="sin" userloc="P2"/><inputs id="rxclk" userloc="P5"/><inputs id="tran" userloc="P3"/><inputs id="txclk" userloc="P6"/><pin id="FB1_MC1_PIN38" pinnum="38"/><pin id="FB1_MC2_PIN37" pinnum="37"/><pin id="FB1_MC3_PIN36" pinnum="36"/><pin id="FB1_MC4_PIN34" pinnum="34"/><pin id="FB1_MC5_PIN33" pinnum="33"/><pin id="FB1_MC6_PIN32" pinnum="32"/><pin id="FB1_MC7_PIN31" pinnum="31"/><pin id="FB1_MC8_PIN30" pinnum="30"/><pin id="FB1_MC9_PIN29" pinnum="29"/><pin id="FB1_MC10_PIN28" pinnum="28"/><pin id="FB1_MC11_PIN27" pinnum="27"/><pin id="FB1_MC12_PIN23" pinnum="23"/><pin id="FB1_MC13_PIN22" pinnum="22"/><pin id="FB1_MC14_PIN21" pinnum="21"/><pin id="FB1_MC15_PIN20" pinnum="20"/><pin id="FB1_MC16_PIN19" pinnum="19"/><pin id="FB2_MC1_PIN39" pinnum="39"/><pin id="FB2_MC2_PIN40" pinnum="40"/><pin id="FB2_MC3_PIN41" pinnum="41"/><pin id="FB2_MC4_PIN42" pinnum="42"/><pin id="FB2_MC5_PIN43" pinnum="43"/><pin id="FB2_MC6_PIN44" pinnum="44"/><pin id="FB2_MC7_PIN1" pinnum="1"/><pin id="FB2_MC8_PIN2" pinnum="2"/><pin id="FB2_MC9_PIN3" pinnum="3"/><pin id="FB2_MC10_PIN5" pinnum="5"/><pin id="FB2_MC11_PIN6" pinnum="6"/><pin id="FB2_MC12_PIN8" pinnum="8"/><pin id="FB2_MC13_PIN12" pinnum="12"/><pin id="FB2_MC14_PIN13" pinnum="13"/><pin id="FB2_MC15_PIN14" pinnum="14"/><pin id="FB2_MC16_PIN16" pinnum="16"/><pin id="FB_PIN35" use="VCCAUX" pinnum="35"/><pin id="FB_PIN7" use="VCCIO-UNUSED" pinnum="7"/><pin id="FB_PIN15" use="VCC" pinnum="15"/><pin id="FB_PIN26" use="VCCIO-UNUSED" pinnum="26"/><failuretable><failsig name="N_PZ_147"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d0_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d1_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d2_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d3_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d4_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d5_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d6_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="d7_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data11_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data12_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data13_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data14_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data15_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data16_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data17_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data18_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="data19_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="fe"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="ldrb"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="ldsr"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff0_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff1_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff2_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff3_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff4_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff5_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff6_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="rxbuff7_SPECSIG"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="sclk"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="state_FFd1"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="state_FFd2"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="state_FFd3"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig><failsig name="state_FFd4"><funcblk id="FB1"><failure unk="ON"/></funcblk><funcblk id="FB2"><failure unk="ON"/></funcblk></failsig></failuretable><fblock id="FB1" pinUse="0"><macrocell id="FB1_MC1" pin="FB1_MC1_PIN38"/><macrocell id="FB1_MC2" pin="FB1_MC2_PIN37"/><macrocell id="FB1_MC3" pin="FB1_MC3_PIN36"/><macrocell id="FB1_MC4" pin="FB1_MC4_PIN34"/><macrocell id="FB1_MC5" pin="FB1_MC5_PIN33"/><macrocell id="FB1_MC6" pin="FB1_MC6_PIN32"/><macrocell id="FB1_MC7" pin="FB1_MC7_PIN31"/><macrocell id="FB1_MC8" pin="FB1_MC8_PIN30"/><macrocell id="FB1_MC9" pin="FB1_MC9_PIN29"/><macrocell id="FB1_MC10" pin="FB1_MC10_PIN28"/><macrocell id="FB1_MC11" pin="FB1_MC11_PIN27"/><macrocell id="FB1_MC12" pin="FB1_MC12_PIN23"/><macrocell id="FB1_MC13" pin="FB1_MC13_PIN22"/><macrocell id="FB1_MC14" pin="FB1_MC14_PIN21"/><macrocell id="FB1_MC15" pin="FB1_MC15_PIN20"/><macrocell id="FB1_MC16" pin="FB1_MC16_PIN19"/><PAL/></fblock><fblock id="FB2" pinUse="0"><macrocell id="FB2_MC1" pin="FB2_MC1_PIN39"/><macrocell id="FB2_MC2" pin="FB2_MC2_PIN40"/><macrocell id="FB2_MC3" pin="FB2_MC3_PIN41"/><macrocell id="FB2_MC4" pin="FB2_MC4_PIN42"/><macrocell id="FB2_MC5" pin="FB2_MC5_PIN43"/><macrocell id="FB2_MC6" pin="FB2_MC6_PIN44"/><macrocell id="FB2_MC7" pin="FB2_MC7_PIN1"/><macrocell id="FB2_MC8" pin="FB2_MC8_PIN2"/><macrocell id="FB2_MC9" pin="FB2_MC9_PIN3"/><macrocell id="FB2_MC10" pin="FB2_MC10_PIN5"/><macrocell id="FB2_MC11" pin="FB2_MC11_PIN6"/><macrocell id="FB2_MC12" pin="FB2_MC12_PIN8"/><macrocell id="FB2_MC13" pin="FB2_MC13_PIN12"/><macrocell id="FB2_MC14" pin="FB2_MC14_PIN13"/><macrocell id="FB2_MC15" pin="FB2_MC15_PIN14"/><macrocell id="FB2_MC16" pin="FB2_MC16_PIN16"/><PAL/></fblock><unmapped_logic><pterm id="INPUTPINS_1_1"><signal id="rxbuff0_SPECSIG"/><signal id="tran" negated="ON"/></pterm><pterm id="INPUTPINS_1_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P28" sigUse="3"><equation id="d0_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_1_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_1_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_2_1"><signal id="data11_SPECSIG"/></pterm><pterm id="INPUTPINS_2_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_2_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P14" sigUse="3"><equation id="rxbuff0_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_2_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_2_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_2_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_3_1"><signal id="data11_SPECSIG" negated="ON"/><signal id="sclk" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_3_2"><signal id="sclk"/><signal id="sin" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_3_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data11_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_3_1"/><eq_pterm ptindx="INPUTPINS_3_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_3_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_4_1"><signal id="sclk"/><signal id="state_FFd4"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_4_2"><signal id="sclk"/><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2" negated="ON"/></pterm><pterm id="INPUTPINS_4_3"><signal id="sclk" negated="ON"/><signal id="state_FFd4"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_4_4"><signal id="sclk" negated="ON"/><signal id="state_FFd4" negated="ON"/><signal id="sin" negated="ON"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_4_5"><signal id="rxclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P8" sigUse="7"><equation id="sclk" regUse="TFF"><d2><eq_pterm ptindx="INPUTPINS_4_1"/><eq_pterm ptindx="INPUTPINS_4_2"/><eq_pterm ptindx="INPUTPINS_4_3"/><eq_pterm ptindx="INPUTPINS_4_4"/></d2><clk><eq_pterm ptindx="INPUTPINS_4_5"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_5_1"><signal id="state_FFd4" negated="ON"/><signal id="sin" negated="ON"/><signal id="state_FFd3" negated="ON"/></pterm><pterm id="INPUTPINS_5_2"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3"/><signal id="state_FFd1" negated="ON"/></pterm><pterm id="INPUTPINS_5_3"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd1"/><signal id="state_FFd2" negated="ON"/></pterm><pterm id="INPUTPINS_5_4"><signal id="state_FFd4"/><signal id="sin" negated="ON"/><signal id="state_FFd1"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_5_5"><signal id="state_FFd4"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_5_6"><signal id="state_FFd3"/><signal id="state_FFd1"/><signal id="state_FFd2" negated="ON"/><signal id="data19_SPECSIG"/></pterm><pterm id="INPUTPINS_5_7"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="7"><equation id="state_FFd4" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_5_1"/><eq_pterm ptindx="INPUTPINS_5_2"/><eq_pterm ptindx="INPUTPINS_5_3"/><eq_pterm ptindx="INPUTPINS_5_4"/><eq_pterm ptindx="INPUTPINS_5_5"/><eq_pterm ptindx="INPUTPINS_5_6"/></d2><clk><eq_pterm ptindx="INPUTPINS_5_7"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_6_1"><signal id="state_FFd4" negated="ON"/></pterm><pterm id="INPUTPINS_6_2"><signal id="state_FFd1"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_6_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="4"><equation id="state_FFd3" regUse="TFF" negated="ON"><d1><eq_pterm ptindx="INPUTPINS_6_1"/></d1><d2><eq_pterm ptindx="INPUTPINS_6_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_6_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_7_1"><signal id="state_FFd1"/><signal id="state_FFd2" negated="ON"/></pterm><pterm id="INPUTPINS_7_2"><signal id="state_FFd4"/><signal id="state_FFd3"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_7_3"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1"/></pterm><pterm id="INPUTPINS_7_4"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="state_FFd1" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_7_1"/><eq_pterm ptindx="INPUTPINS_7_2"/><eq_pterm ptindx="INPUTPINS_7_3"/></d2><clk><eq_pterm ptindx="INPUTPINS_7_4"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_8_1"><signal id="state_FFd4"/><signal id="state_FFd3"/></pterm><pterm id="INPUTPINS_8_2"><signal id="state_FFd3"/><signal id="state_FFd1"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_8_3"><signal id="state_FFd4" negated="ON"/><signal id="sin"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2"/></pterm><pterm id="INPUTPINS_8_4"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="6"><equation id="state_FFd2" regUse="TFF"><d1><eq_pterm ptindx="INPUTPINS_8_1"/></d1><d2><eq_pterm ptindx="INPUTPINS_8_2"/><eq_pterm ptindx="INPUTPINS_8_3"/></d2><clk><eq_pterm ptindx="INPUTPINS_8_4"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_9_1"><signal id="sclk"/><signal id="data18_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_9_2"><signal id="sclk" negated="ON"/><signal id="data19_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_9_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data19_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_9_1"/><eq_pterm ptindx="INPUTPINS_9_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_9_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_10_1"><signal id="sclk"/><signal id="data17_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_10_2"><signal id="sclk" negated="ON"/><signal id="data18_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_10_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data18_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_10_1"/><eq_pterm ptindx="INPUTPINS_10_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_10_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_11_1"><signal id="sclk"/><signal id="data16_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_11_2"><signal id="sclk" negated="ON"/><signal id="data17_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_11_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data17_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_11_1"/><eq_pterm ptindx="INPUTPINS_11_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_11_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_12_1"><signal id="sclk"/><signal id="data15_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_12_2"><signal id="sclk" negated="ON"/><signal id="data16_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_12_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data16_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_12_1"/><eq_pterm ptindx="INPUTPINS_12_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_12_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_13_1"><signal id="sclk"/><signal id="data14_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_13_2"><signal id="sclk" negated="ON"/><signal id="data15_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_13_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data15_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_13_1"/><eq_pterm ptindx="INPUTPINS_13_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_13_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_14_1"><signal id="sclk"/><signal id="data13_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_14_2"><signal id="sclk" negated="ON"/><signal id="data14_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_14_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data14_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_14_1"/><eq_pterm ptindx="INPUTPINS_14_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_14_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_15_1"><signal id="sclk"/><signal id="data12_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_15_2"><signal id="sclk" negated="ON"/><signal id="data13_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_15_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data13_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_15_1"/><eq_pterm ptindx="INPUTPINS_15_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_15_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_16_1"><signal id="data11_SPECSIG" negated="ON"/><signal id="sclk"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_16_2"><signal id="sclk" negated="ON"/><signal id="data12_SPECSIG" negated="ON"/><signal id="N_PZ_147" negated="ON"/></pterm><pterm id="INPUTPINS_16_3"><signal id="rxclk"/></pterm><unmapped_eqn sigUse="5"><equation id="data12_SPECSIG" regUse="DFF" negated="ON"><d2><eq_pterm ptindx="INPUTPINS_16_1"/><eq_pterm ptindx="INPUTPINS_16_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_16_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_17_1"><signal id="sclk" negated="ON"/><signal id="ldsr"/></pterm><pterm id="INPUTPINS_17_2"><signal id="sclk" negated="ON"/><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2" negated="ON"/></pterm><unmapped_eqn sigUse="6"><equation id="N_PZ_147"><d2><eq_pterm ptindx="INPUTPINS_17_1"/><eq_pterm ptindx="INPUTPINS_17_2"/></d2></equation></unmapped_eqn><pterm id="INPUTPINS_18_1"><signal id="state_FFd4"/><signal id="state_FFd3"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2" negated="ON"/><signal id="ldsr"/></pterm><pterm id="INPUTPINS_18_2"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2" negated="ON"/><signal id="ldsr" negated="ON"/></pterm><pterm id="INPUTPINS_18_3"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2" negated="ON"/><signal id="ldsr"/></pterm><pterm id="INPUTPINS_18_4"><signal id="rxclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P12" sigUse="6"><equation id="ldsr" regUse="TFF"><d2><eq_pterm ptindx="INPUTPINS_18_1"/><eq_pterm ptindx="INPUTPINS_18_2"/><eq_pterm ptindx="INPUTPINS_18_3"/></d2><clk><eq_pterm ptindx="INPUTPINS_18_4"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_19_1"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3"/><signal id="state_FFd1"/><signal id="state_FFd2"/><signal id="ldrb" negated="ON"/></pterm><pterm id="INPUTPINS_19_2"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2" negated="ON"/><signal id="ldrb"/></pterm><pterm id="INPUTPINS_19_3"><signal id="rxclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P13" sigUse="6"><equation id="ldrb" regUse="TFF"><d2><eq_pterm ptindx="INPUTPINS_19_1"/><eq_pterm ptindx="INPUTPINS_19_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_19_3"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_20_1"><signal id="tran" negated="ON"/><signal id="rxbuff1_SPECSIG"/></pterm><pterm id="INPUTPINS_20_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P27" sigUse="3"><equation id="d1_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_20_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_20_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_21_1"><signal id="data12_SPECSIG"/></pterm><pterm id="INPUTPINS_21_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_21_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P42" sigUse="3"><equation id="rxbuff1_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_21_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_21_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_21_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_22_1"><signal id="tran" negated="ON"/><signal id="rxbuff2_SPECSIG"/></pterm><pterm id="INPUTPINS_22_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P23" sigUse="3"><equation id="d2_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_22_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_22_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_23_1"><signal id="data13_SPECSIG"/></pterm><pterm id="INPUTPINS_23_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_23_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P40" sigUse="3"><equation id="rxbuff2_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_23_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_23_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_23_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_24_1"><signal id="tran" negated="ON"/><signal id="rxbuff3_SPECSIG"/></pterm><pterm id="INPUTPINS_24_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P22" sigUse="3"><equation id="d3_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_24_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_24_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_25_1"><signal id="data14_SPECSIG"/></pterm><pterm id="INPUTPINS_25_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_25_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P39" sigUse="3"><equation id="rxbuff3_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_25_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_25_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_25_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_26_1"><signal id="tran" negated="ON"/><signal id="rxbuff4_SPECSIG"/></pterm><pterm id="INPUTPINS_26_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P21" sigUse="3"><equation id="d4_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_26_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_26_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_27_1"><signal id="data15_SPECSIG"/></pterm><pterm id="INPUTPINS_27_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_27_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P38" sigUse="3"><equation id="rxbuff4_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_27_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_27_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_27_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_28_1"><signal id="tran" negated="ON"/><signal id="rxbuff5_SPECSIG"/></pterm><pterm id="INPUTPINS_28_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P20" sigUse="3"><equation id="d5_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_28_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_28_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_29_1"><signal id="data16_SPECSIG"/></pterm><pterm id="INPUTPINS_29_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_29_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P37" sigUse="3"><equation id="rxbuff5_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_29_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_29_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_29_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_30_1"><signal id="tran" negated="ON"/><signal id="rxbuff6_SPECSIG"/></pterm><pterm id="INPUTPINS_30_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P19" sigUse="3"><equation id="d6_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_30_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_30_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_31_1"><signal id="data17_SPECSIG"/></pterm><pterm id="INPUTPINS_31_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_31_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P36" sigUse="3"><equation id="rxbuff6_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_31_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_31_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_31_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_32_1"><signal id="tran" negated="ON"/><signal id="rxbuff7_SPECSIG"/></pterm><pterm id="INPUTPINS_32_2"><signal id="txclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P16" sigUse="3"><equation id="d7_SPECSIG" regUse="DFF"><d2><eq_pterm ptindx="INPUTPINS_32_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_32_2"/></clk></equation></unmapped_eqn><pterm id="INPUTPINS_33_1"><signal id="data18_SPECSIG"/></pterm><pterm id="INPUTPINS_33_2"><signal id="rxclk"/></pterm><pterm id="INPUTPINS_33_3"><signal id="ldrb"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P29" sigUse="3"><equation id="rxbuff7_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="INPUTPINS_33_1"/></d2><clk><eq_pterm ptindx="INPUTPINS_33_2"/></clk><ce><eq_pterm ptindx="INPUTPINS_33_3"/></ce></equation></unmapped_eqn><pterm id="INPUTPINS_34_1"><signal id="state_FFd4"/><signal id="state_FFd3"/><signal id="state_FFd1"/><signal id="state_FFd2"/><signal id="fe" negated="ON"/></pterm><pterm id="INPUTPINS_34_2"><signal id="state_FFd4" negated="ON"/><signal id="state_FFd3" negated="ON"/><signal id="state_FFd1" negated="ON"/><signal id="state_FFd2" negated="ON"/><signal id="fe"/></pterm><pterm id="INPUTPINS_34_3"><signal id="rxclk"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" pinnum="P41" sigUse="6"><equation id="fe" regUse="TFF"><d2><eq_pterm ptindx="INPUTPINS_34_1"/><eq_pterm ptindx="INPUTPINS_34_2"/></d2><clk><eq_pterm ptindx="INPUTPINS_34_3"/></clk></equation></unmapped_eqn><unmapped_input id="sin" pinnum="P2"/><unmapped_input id="rxclk" pinnum="P5"/><unmapped_input id="tran" pinnum="P3"/><unmapped_input id="txclk" pinnum="P6"/></unmapped_logic><vcc/><gnd/><messages><error>Cpld:1063 - Design requires at least 34 macrocells, exceeds device limit   32.</error><error>Cpld:1064 - Design rules checking error. Fitting process stopped.</error><warning>Cpld:868 - Cannot fit the design into any of the specified devices with   the selected implementation options.</warning></messages><compOpts loc="ON" part="xa2c32a-6-VQ44" prld="LOW" slew="FAST" inreg="ON" iostd="LVCMOS18" mlopt="ON" gsropt="ON" gtsopt="ON" inputs="32" keepio="OFF" pterms="28" unused="KEEPER" exhaust="OFF" gclkopt="ON" wysiwyg="OFF" blkfanin="38" datagate="ON" ignoredg="OFF" ignorets="OFF" optimize="DENSITY" terminate="KEEPER"/><specSig value="d&lt;0&gt;" signal="d0_SPECSIG"/><specSig value="d&lt;1&gt;" signal="d1_SPECSIG"/><specSig value="d&lt;2&gt;" signal="d2_SPECSIG"/><specSig value="d&lt;3&gt;" signal="d3_SPECSIG"/><specSig value="d&lt;4&gt;" signal="d4_SPECSIG"/><specSig value="d&lt;5&gt;" signal="d5_SPECSIG"/><specSig value="d&lt;6&gt;" signal="d6_SPECSIG"/><specSig value="d&lt;7&gt;" signal="d7_SPECSIG"/><specSig value="data1&lt;1&gt;" signal="data11_SPECSIG"/><specSig value="data1&lt;2&gt;" signal="data12_SPECSIG"/><specSig value="data1&lt;3&gt;" signal="data13_SPECSIG"/><specSig value="data1&lt;4&gt;" signal="data14_SPECSIG"/><specSig value="data1&lt;5&gt;" signal="data15_SPECSIG"/><specSig value="data1&lt;6&gt;" signal="data16_SPECSIG"/><specSig value="data1&lt;7&gt;" signal="data17_SPECSIG"/><specSig value="data1&lt;8&gt;" signal="data18_SPECSIG"/><specSig value="data1&lt;9&gt;" signal="data19_SPECSIG"/><specSig value="rxbuff&lt;0&gt;" signal="rxbuff0_SPECSIG"/><specSig value="rxbuff&lt;1&gt;" signal="rxbuff1_SPECSIG"/><specSig value="rxbuff&lt;2&gt;" signal="rxbuff2_SPECSIG"/><specSig value="rxbuff&lt;3&gt;" signal="rxbuff3_SPECSIG"/><specSig value="rxbuff&lt;4&gt;" signal="rxbuff4_SPECSIG"/><specSig value="rxbuff&lt;5&gt;" signal="rxbuff5_SPECSIG"/><specSig value="rxbuff&lt;6&gt;" signal="rxbuff6_SPECSIG"/><specSig value="rxbuff&lt;7&gt;" signal="rxbuff7_SPECSIG"/></document>