📄 defeqns.htm
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<h3 align='center'>Equations</h3>
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********** UnMapped Logic **********
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** Outputs **
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FDCPE_d0: FDCPE port map (d(0),d_D(0),txclk,'0','0','1');
<br/> d_D(0) <= (rxbuff(0) AND NOT tran);
</td></tr><tr><td>
FDCPE_d1: FDCPE port map (d(1),d_D(1),txclk,'0','0','1');
<br/> d_D(1) <= (NOT tran AND rxbuff(1));
</td></tr><tr><td>
FDCPE_d2: FDCPE port map (d(2),d_D(2),txclk,'0','0','1');
<br/> d_D(2) <= (NOT tran AND rxbuff(2));
</td></tr><tr><td>
FDCPE_d3: FDCPE port map (d(3),d_D(3),txclk,'0','0','1');
<br/> d_D(3) <= (NOT tran AND rxbuff(3));
</td></tr><tr><td>
FDCPE_d4: FDCPE port map (d(4),d_D(4),txclk,'0','0','1');
<br/> d_D(4) <= (NOT tran AND rxbuff(4));
</td></tr><tr><td>
FDCPE_d5: FDCPE port map (d(5),d_D(5),txclk,'0','0','1');
<br/> d_D(5) <= (NOT tran AND rxbuff(5));
</td></tr><tr><td>
FDCPE_d6: FDCPE port map (d(6),d_D(6),txclk,'0','0','1');
<br/> d_D(6) <= (NOT tran AND rxbuff(6));
</td></tr><tr><td>
FDCPE_d7: FDCPE port map (d(7),d_D(7),txclk,'0','0','1');
<br/> d_D(7) <= (NOT tran AND rxbuff(7));
</td></tr><tr><td>
FTCPE_fe: FTCPE port map (fe,fe_T,rxclk,'0','0','1');
<br/> fe_T <= ((state_FFd4 AND state_FFd3 AND state_FFd1 AND
<br/> state_FFd2 AND NOT fe)
<br/> OR (NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
<br/> NOT state_FFd2 AND fe));
</td></tr><tr><td>
FTCPE_ldrb: FTCPE port map (ldrb,ldrb_T,rxclk,'0','0','1');
<br/> ldrb_T <= ((NOT state_FFd4 AND state_FFd3 AND state_FFd1 AND
<br/> state_FFd2 AND NOT ldrb)
<br/> OR (NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
<br/> NOT state_FFd2 AND ldrb));
</td></tr><tr><td>
FTCPE_ldsr: FTCPE port map (ldsr,ldsr_T,rxclk,'0','0','1');
<br/> ldsr_T <= ((state_FFd4 AND state_FFd3 AND NOT state_FFd1 AND
<br/> NOT state_FFd2 AND ldsr)
<br/> OR (NOT state_FFd4 AND state_FFd3 AND NOT state_FFd1 AND
<br/> NOT state_FFd2 AND NOT ldsr)
<br/> OR (NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
<br/> NOT state_FFd2 AND ldsr));
</td></tr><tr><td>
FDCPE_rxbuff0: FDCPE port map (rxbuff(0),data1(1),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FDCPE_rxbuff1: FDCPE port map (rxbuff(1),data1(2),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FDCPE_rxbuff2: FDCPE port map (rxbuff(2),data1(3),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FDCPE_rxbuff3: FDCPE port map (rxbuff(3),data1(4),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FDCPE_rxbuff4: FDCPE port map (rxbuff(4),data1(5),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FDCPE_rxbuff5: FDCPE port map (rxbuff(5),data1(6),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FDCPE_rxbuff6: FDCPE port map (rxbuff(6),data1(7),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FDCPE_rxbuff7: FDCPE port map (rxbuff(7),data1(8),rxclk,'0','0',ldrb);
</td></tr><tr><td>
FTCPE_sclk: FTCPE port map (sclk,sclk_T,rxclk,'0','0','1');
<br/> sclk_T <= ((sclk AND state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
<br/> state_FFd2)
<br/> OR (sclk AND NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
<br/> NOT state_FFd2)
<br/> OR (NOT sclk AND state_FFd4 AND NOT state_FFd3 AND state_FFd1 AND
<br/> state_FFd2)
<br/> OR (NOT sclk AND NOT state_FFd4 AND NOT sin AND NOT state_FFd3 AND
<br/> NOT state_FFd1 AND state_FFd2));
</td></tr><tr><td>
** Buried Nodes **
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_147 <= ((NOT sclk AND ldsr)
<br/> OR (NOT sclk AND NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
<br/> NOT state_FFd2));
</td></tr><tr><td>
FDCPE_data11: FDCPE port map (data1(1),data1_D(1),rxclk,'0','0','1');
<br/> data1_D(1) <= NOT (((NOT data1(1) AND NOT sclk AND NOT N_PZ_147)
<br/> OR (sclk AND NOT sin AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data12: FDCPE port map (data1(2),data1_D(2),rxclk,'0','0','1');
<br/> data1_D(2) <= NOT (((NOT data1(1) AND sclk AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(2) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data13: FDCPE port map (data1(3),data1_D(3),rxclk,'0','0','1');
<br/> data1_D(3) <= NOT (((sclk AND NOT data1(2) AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(3) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data14: FDCPE port map (data1(4),data1_D(4),rxclk,'0','0','1');
<br/> data1_D(4) <= NOT (((sclk AND NOT data1(3) AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(4) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data15: FDCPE port map (data1(5),data1_D(5),rxclk,'0','0','1');
<br/> data1_D(5) <= NOT (((sclk AND NOT data1(4) AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(5) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data16: FDCPE port map (data1(6),data1_D(6),rxclk,'0','0','1');
<br/> data1_D(6) <= NOT (((sclk AND NOT data1(5) AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(6) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data17: FDCPE port map (data1(7),data1_D(7),rxclk,'0','0','1');
<br/> data1_D(7) <= NOT (((sclk AND NOT data1(6) AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(7) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data18: FDCPE port map (data1(8),data1_D(8),rxclk,'0','0','1');
<br/> data1_D(8) <= NOT (((sclk AND NOT data1(7) AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(8) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_data19: FDCPE port map (data1(9),data1_D(9),rxclk,'0','0','1');
<br/> data1_D(9) <= NOT (((sclk AND NOT data1(8) AND NOT N_PZ_147)
<br/> OR (NOT sclk AND NOT data1(9) AND NOT N_PZ_147)));
</td></tr><tr><td>
FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,rxclk,'0','0','1');
<br/> state_FFd1_D <= ((state_FFd1 AND NOT state_FFd2)
<br/> OR (state_FFd4 AND state_FFd3 AND state_FFd2)
<br/> OR (NOT state_FFd4 AND NOT state_FFd3 AND state_FFd1));
</td></tr><tr><td>
FTCPE_state_FFd2: FTCPE port map (state_FFd2,state_FFd2_T,rxclk,'0','0','1');
<br/> state_FFd2_T <= (state_FFd4 AND state_FFd3)
<br/> XOR ((state_FFd3 AND state_FFd1 AND state_FFd2)
<br/> OR (NOT state_FFd4 AND sin AND NOT state_FFd3 AND NOT state_FFd1 AND
<br/> state_FFd2));
</td></tr><tr><td>
FTCPE_state_FFd3: FTCPE port map (state_FFd3,state_FFd3_T,rxclk,'0','0','1');
<br/> state_FFd3_T <= NOT (NOT state_FFd4
<br/> XOR (state_FFd1 AND state_FFd2));
</td></tr><tr><td>
FDCPE_state_FFd4: FDCPE port map (state_FFd4,state_FFd4_D,rxclk,'0','0','1');
<br/> state_FFd4_D <= ((NOT state_FFd4 AND NOT sin AND NOT state_FFd3)
<br/> OR (NOT state_FFd4 AND state_FFd3 AND NOT state_FFd1)
<br/> OR (NOT state_FFd4 AND state_FFd1 AND NOT state_FFd2)
<br/> OR (state_FFd4 AND NOT sin AND state_FFd1 AND state_FFd2)
<br/> OR (state_FFd4 AND NOT state_FFd3 AND state_FFd1 AND
<br/> state_FFd2)
<br/> OR (state_FFd3 AND state_FFd1 AND NOT state_FFd2 AND data1(9)));
</td></tr><tr><td>
</td></tr><tr><td>
Register Legend:
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
<br/> FDDCPE (Q,D,C,CLR,PRE,CE);
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
<br/> FTDCPE (Q,D,C,CLR,PRE,CE);
<br/> LDCP (Q,D,G,CLR,PRE);
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</td></tr>
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