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<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='logiclegend.htm'" value="brief"></form></td></tr></table>
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<th width="20%">Acronym</th>
<th width="80%">Verbose Description</th>
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<td width="20%">聽*</td>
<td width="80%">聽User Assigned</td>
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<td width="20%">聽(b)</td>
<td width="80%">聽Buried macrocell</td>
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<td width="20%">聽CTC</td>
<td width="80%">聽Control Term Clock</td>
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<td width="20%">聽CTR</td>
<td width="80%">聽Control Term Reset</td>
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<td width="20%">聽CTS</td>
<td width="80%">聽Control Term Set</td>
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<td width="20%">聽CTE</td>
<td width="80%">聽Control Term Output Enable</td>
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<td width="20%">聽DFF</td>
<td width="80%">聽D Flip-Flop</td>
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<td width="20%">聽DDFF</td>
<td width="80%">聽Dual-edge triggered D Flip-Flop</td>
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<td width="20%">聽DEFF</td>
<td width="80%">聽D Flip-Flop with Enable</td>
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<td width="20%">聽DDEFF</td>
<td width="80%">聽Dual-edge triggered D Flip-Flop with Enable</td>
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<td width="20%">聽DG</td>
<td width="80%">聽DataGATE</td>
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<td width="20%">聽DGE</td>
<td width="80%">聽DataGATE Enable</td>
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<td width="20%">聽FB#</td>
<td width="80%">聽Function Block number</td>
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<td width="20%">聽GCK#</td>
<td width="80%">聽Global Clock number</td>
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<td width="20%">聽GTS#</td>
<td width="80%">聽Global Output Enable number</td>
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<td width="20%">聽GSR</td>
<td width="80%">聽Global Set/Reset</td>
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<td width="20%">聽I</td>
<td width="80%">聽Input</td>
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<td width="20%">聽I/O</td>
<td width="80%">聽Input/Output</td>
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<td width="20%">聽IR</td>
<td width="80%">聽Direct Input Register</td>
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<td width="20%">聽KPR</td>
<td width="80%">聽Unused I/O with weak keeper (leave unconnected)</td>
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<td width="20%">聽Latch</td>
<td width="80%">聽Transparent latch</td>
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<td width="20%">聽MC#</td>
<td width="80%">聽Macrocell number</td>
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<td width="20%">聽O</td>
<td width="80%">聽Output</td>
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<td width="20%">聽OD</td>
<td width="80%">聽Open Drain</td>
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<td width="20%">聽PU</td>
<td width="80%">聽Pullup</td>
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<td width="20%">聽/S</td>
<td width="80%">聽After any flop/latch type indicates initial state is Set</td>
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<td width="20%">聽TCK</td>
<td width="80%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.</td>
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<td width="20%">聽TDI</td>
<td width="80%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.</td>
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<td width="20%">聽TDO</td>
<td width="80%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.</td>
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<td width="20%">聽TFF</td>
<td width="80%">聽Toggle Flip-Flop</td>
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<td width="20%">聽TDFF</td>
<td width="80%">聽Dual edge triggered Toggle Flip-Flop</td>
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<td width="20%">聽TMS</td>
<td width="80%">聽One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532. </td>
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<td width="20%">聽VREF</td>
<td width="80%">聽Pin used to compare to an external voltage reference for high speed I/O Standards.</td>
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