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cpldfit: version H.42 Xilinx Inc.
No Fit Report
Design Name: yibutongxin Date: 3-27-2007, 11:46AM
Device Used: XA2C32A-6-VQ44
Fitting Status: Design Rule Checking Failed
************************** Errors and Warnings ***************************
ERROR:Cpld:1063 - Design requires at least 34 macrocells, exceeds device limit
32.
ERROR:Cpld:1064 - Design rules checking error. Fitting process stopped.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
************************* Mapped Resource Summary **************************
No logic has been mapped.
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
0 /32 ( 0%) 0 /112 ( 0%) 0 /80 ( 0%) 0 /32 ( 0%) 0 /33 ( 0%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO CTC CTR CTS CTE
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 0/16 0/40 0/56 0/16 0/1 0/1 0/1 0/1
FB2 0/16 0/40 0/56 0/16 0/1 0/1 0/1 0/1
----- ------- ------- ----- --- --- --- ---
Total 0/32 0/80 0/112 0/32 0/2 0/2 0/2 0/2
CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable
* - Resource is exhausted
** Global Control Resources **
GCK GSR GTS
Used/Tot Used/Tot Used/Tot
0/3 0/1 0/4
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
| I : 0 1
Input : 4 0 | I/O : 0 24
Output : 20 0 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 24 0
End of Mapped Resource Summary
************************* Summary of UnMapped Logic ************************
** 20 Outputs **
Signal Total Total I/O User
Name Pts Inps STD Assignment
d<0> 2 3 LVCMOS18 P28
d<1> 2 3 LVCMOS18 P27
d<2> 2 3 LVCMOS18 P23
d<3> 2 3 LVCMOS18 P22
d<4> 2 3 LVCMOS18 P21
d<5> 2 3 LVCMOS18 P20
d<6> 2 3 LVCMOS18 P19
d<7> 2 3 LVCMOS18 P16
fe 3 6 LVCMOS18 P41
ldrb 3 6 LVCMOS18 P13
ldsr 4 6 LVCMOS18 P12
rxbuff<0> 3 3 LVCMOS18 P14
rxbuff<1> 3 3 LVCMOS18 P42
rxbuff<2> 3 3 LVCMOS18 P40
rxbuff<3> 3 3 LVCMOS18 P39
rxbuff<4> 3 3 LVCMOS18 P38
rxbuff<5> 3 3 LVCMOS18 P37
rxbuff<6> 3 3 LVCMOS18 P36
rxbuff<7> 3 3 LVCMOS18 P29
sclk 5 7 LVCMOS18 P8
** 14 Buried Nodes **
Signal Total Total User
Name Pts Inps Assignment
N_PZ_147 2 6
data1<1> 3 5
data1<2> 3 5
data1<3> 3 5
data1<4> 3 5
data1<5> 3 5
data1<6> 3 5
data1<7> 3 5
data1<8> 3 5
data1<9> 3 5
state_FFd1 4 5
state_FFd2 4 6
state_FFd3 3 4
state_FFd4 7 7
** 4 Inputs **
Signal I/O User
Name STD Assignment
rxclk LVCMOS18 P5
sin LVCMOS18 P2
tran LVCMOS18 P3
txclk LVCMOS18 P6
******************************* Equations ********************************
********** UnMapped Logic **********
** Outputs **
FDCPE_d0: FDCPE port map (d(0),d_D(0),txclk,'0','0','1');
d_D(0) <= (rxbuff(0) AND NOT tran);
FDCPE_d1: FDCPE port map (d(1),d_D(1),txclk,'0','0','1');
d_D(1) <= (NOT tran AND rxbuff(1));
FDCPE_d2: FDCPE port map (d(2),d_D(2),txclk,'0','0','1');
d_D(2) <= (NOT tran AND rxbuff(2));
FDCPE_d3: FDCPE port map (d(3),d_D(3),txclk,'0','0','1');
d_D(3) <= (NOT tran AND rxbuff(3));
FDCPE_d4: FDCPE port map (d(4),d_D(4),txclk,'0','0','1');
d_D(4) <= (NOT tran AND rxbuff(4));
FDCPE_d5: FDCPE port map (d(5),d_D(5),txclk,'0','0','1');
d_D(5) <= (NOT tran AND rxbuff(5));
FDCPE_d6: FDCPE port map (d(6),d_D(6),txclk,'0','0','1');
d_D(6) <= (NOT tran AND rxbuff(6));
FDCPE_d7: FDCPE port map (d(7),d_D(7),txclk,'0','0','1');
d_D(7) <= (NOT tran AND rxbuff(7));
FTCPE_fe: FTCPE port map (fe,fe_T,rxclk,'0','0','1');
fe_T <= ((state_FFd4 AND state_FFd3 AND state_FFd1 AND
state_FFd2 AND NOT fe)
OR (NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
NOT state_FFd2 AND fe));
FTCPE_ldrb: FTCPE port map (ldrb,ldrb_T,rxclk,'0','0','1');
ldrb_T <= ((NOT state_FFd4 AND state_FFd3 AND state_FFd1 AND
state_FFd2 AND NOT ldrb)
OR (NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
NOT state_FFd2 AND ldrb));
FTCPE_ldsr: FTCPE port map (ldsr,ldsr_T,rxclk,'0','0','1');
ldsr_T <= ((state_FFd4 AND state_FFd3 AND NOT state_FFd1 AND
NOT state_FFd2 AND ldsr)
OR (NOT state_FFd4 AND state_FFd3 AND NOT state_FFd1 AND
NOT state_FFd2 AND NOT ldsr)
OR (NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
NOT state_FFd2 AND ldsr));
FDCPE_rxbuff0: FDCPE port map (rxbuff(0),data1(1),rxclk,'0','0',ldrb);
FDCPE_rxbuff1: FDCPE port map (rxbuff(1),data1(2),rxclk,'0','0',ldrb);
FDCPE_rxbuff2: FDCPE port map (rxbuff(2),data1(3),rxclk,'0','0',ldrb);
FDCPE_rxbuff3: FDCPE port map (rxbuff(3),data1(4),rxclk,'0','0',ldrb);
FDCPE_rxbuff4: FDCPE port map (rxbuff(4),data1(5),rxclk,'0','0',ldrb);
FDCPE_rxbuff5: FDCPE port map (rxbuff(5),data1(6),rxclk,'0','0',ldrb);
FDCPE_rxbuff6: FDCPE port map (rxbuff(6),data1(7),rxclk,'0','0',ldrb);
FDCPE_rxbuff7: FDCPE port map (rxbuff(7),data1(8),rxclk,'0','0',ldrb);
FTCPE_sclk: FTCPE port map (sclk,sclk_T,rxclk,'0','0','1');
sclk_T <= ((sclk AND state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
state_FFd2)
OR (sclk AND NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
NOT state_FFd2)
OR (NOT sclk AND state_FFd4 AND NOT state_FFd3 AND state_FFd1 AND
state_FFd2)
OR (NOT sclk AND NOT state_FFd4 AND NOT sin AND NOT state_FFd3 AND
NOT state_FFd1 AND state_FFd2));
** Buried Nodes **
N_PZ_147 <= ((NOT sclk AND ldsr)
OR (NOT sclk AND NOT state_FFd4 AND NOT state_FFd3 AND NOT state_FFd1 AND
NOT state_FFd2));
FDCPE_data11: FDCPE port map (data1(1),data1_D(1),rxclk,'0','0','1');
data1_D(1) <= NOT (((NOT data1(1) AND NOT sclk AND NOT N_PZ_147)
OR (sclk AND NOT sin AND NOT N_PZ_147)));
FDCPE_data12: FDCPE port map (data1(2),data1_D(2),rxclk,'0','0','1');
data1_D(2) <= NOT (((NOT data1(1) AND sclk AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(2) AND NOT N_PZ_147)));
FDCPE_data13: FDCPE port map (data1(3),data1_D(3),rxclk,'0','0','1');
data1_D(3) <= NOT (((sclk AND NOT data1(2) AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(3) AND NOT N_PZ_147)));
FDCPE_data14: FDCPE port map (data1(4),data1_D(4),rxclk,'0','0','1');
data1_D(4) <= NOT (((sclk AND NOT data1(3) AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(4) AND NOT N_PZ_147)));
FDCPE_data15: FDCPE port map (data1(5),data1_D(5),rxclk,'0','0','1');
data1_D(5) <= NOT (((sclk AND NOT data1(4) AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(5) AND NOT N_PZ_147)));
FDCPE_data16: FDCPE port map (data1(6),data1_D(6),rxclk,'0','0','1');
data1_D(6) <= NOT (((sclk AND NOT data1(5) AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(6) AND NOT N_PZ_147)));
FDCPE_data17: FDCPE port map (data1(7),data1_D(7),rxclk,'0','0','1');
data1_D(7) <= NOT (((sclk AND NOT data1(6) AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(7) AND NOT N_PZ_147)));
FDCPE_data18: FDCPE port map (data1(8),data1_D(8),rxclk,'0','0','1');
data1_D(8) <= NOT (((sclk AND NOT data1(7) AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(8) AND NOT N_PZ_147)));
FDCPE_data19: FDCPE port map (data1(9),data1_D(9),rxclk,'0','0','1');
data1_D(9) <= NOT (((sclk AND NOT data1(8) AND NOT N_PZ_147)
OR (NOT sclk AND NOT data1(9) AND NOT N_PZ_147)));
FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,rxclk,'0','0','1');
state_FFd1_D <= ((state_FFd1 AND NOT state_FFd2)
OR (state_FFd4 AND state_FFd3 AND state_FFd2)
OR (NOT state_FFd4 AND NOT state_FFd3 AND state_FFd1));
FTCPE_state_FFd2: FTCPE port map (state_FFd2,state_FFd2_T,rxclk,'0','0','1');
state_FFd2_T <= (state_FFd4 AND state_FFd3)
XOR ((state_FFd3 AND state_FFd1 AND state_FFd2)
OR (NOT state_FFd4 AND sin AND NOT state_FFd3 AND NOT state_FFd1 AND
state_FFd2));
FTCPE_state_FFd3: FTCPE port map (state_FFd3,state_FFd3_T,rxclk,'0','0','1');
state_FFd3_T <= NOT (NOT state_FFd4
XOR (state_FFd1 AND state_FFd2));
FDCPE_state_FFd4: FDCPE port map (state_FFd4,state_FFd4_D,rxclk,'0','0','1');
state_FFd4_D <= ((NOT state_FFd4 AND NOT sin AND NOT state_FFd3)
OR (NOT state_FFd4 AND state_FFd3 AND NOT state_FFd1)
OR (NOT state_FFd4 AND state_FFd1 AND NOT state_FFd2)
OR (state_FFd4 AND NOT sin AND state_FFd1 AND state_FFd2)
OR (state_FFd4 AND NOT state_FFd3 AND state_FFd1 AND
state_FFd2)
OR (state_FFd3 AND state_FFd1 AND NOT state_FFd2 AND data1(9)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FDDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xa2c32a-6-VQ44
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Use DATA_GATE Attribute : ON
Set Tristate Outputs to Termination Mode : KEEPER
Default Voltage Standard for All Outputs : LVCMOS18
Input Limit : 32
Pterm Limit : 28
</pre>
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