2x8bit_dac.v

来自「用EPM7032（CPLD）做的２路８位并行输入ＤＡＣ」· Verilog 代码 · 共 48 行

//2way8bitdac
 module  dac(data1,data2,clk,clk1,co1,co2); 
   input[7:0]  data1,data2;
   output  co1,co2,clk,clk1;
   wire   en,clk,clk1;   
   wire [4:0]  d;
   reg    co1,co2;
   reg[3:0] count;
   reg[7:0] count1;

assign  en=1;               //INOSC
assign  d[0]=~(d[4] & en);
assign  d[1]=d[0] & en;
assign  d[2]=~(d[1] & en);
assign  d[3]=d[2] & en;
assign  d[4]=~(d[3] & en);
assign  clk=d[4];
assign  clk1=~count[3];

always @(posedge clk)
 begin 
   count=count+1;
end
 
always @(posedge clk1)
 begin 
   count1=count1+1;
   if(data1==0) co1=0;
 else 
 begin
   if(data1==255) co1=1;
  else
  begin
   if(count1<=data1)   co1=1;
   else co1=0;  end
 end

  if(data2==0) co2=0;
 else 
 begin
   if(data2==255) co2=1;
  else
  begin
   if(count1<=data2)   co2=1;
   else co2=0;  end
 end
end
endmodule