io_lvds_synplify.vhd

基于VHDL语言的低压差分接口规范的实现

  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_LDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDC_LVDS is
  port (
    D, T, G, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_LDC_LVDS;

architecture lvds_buff0 of OBUFTDS_LDC_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => CLR, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_LDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDCE_LVDS is
  port (
    D, T, GE, G, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_LDCE_LVDS;

architecture lvds_buff0 of OBUFTDS_LDCE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_LDCE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDP_LVDS is
  port (
    D, T, G, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_LDP_LVDS;

architecture lvds_buff0 of OBUFTDS_LDP_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDP port map (D => D, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDC port map (D => D_n, G => G, CLR => PRE, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => PRE, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_LDP_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDPE_LVDS is
  port (
    D, T, GE, G, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_LDPE_LVDS;

architecture lvds_buff0 of OBUFTDS_LDPE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDPE port map (D => D, GE => GE, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDCE port map (D => D_n, GE => GE, G => G, CLR => PRE, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => PRE, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_LDPE_LVDS

-- *********************************
-- Start of the Input/Output Buffers
-- IO Buffer Flipflops
-- *********************************

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FD_LVDS is
  port (
    D, T, C : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
  attribute syn_preserve of Q : signal is true;
  attribute syn_preserve of IO, IOB : signal is true;
end entity IOBUFDS_FD_LVDS;

architecture lvds_buff0 of IOBUFDS_FD_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  iff_p : FD port map (D => i_p, C => C, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDE_LVDS is
  port (
    D, T, CE, C : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
  attribute syn_preserve of Q : signal is true;
  attribute syn_preserve of IO, IOB : signal is true;
end entity IOBUFDS_FDE_LVDS;

architecture lvds_buff0 of IOBUFDS_FDE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  iff_p : FDE port map (D => i_p, CE => CE, C => C, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDC_LVDS is
  port (
    D, T, C, CLR : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
  attribute syn_preserve of Q : signal is true;
  attribute syn_preserve of IO, IOB : signal is true;
end entity IOBUFDS_FDC_LVDS;

architecture lvds_buff0 of IOBUFDS_FDC_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  iff_p : FDC port map (D => i_p, C => C, CLR => CLR, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDCE_LVDS is
  port (
    D, T, CE, C, CLR : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
  attribute syn_preserve of Q : signal is true;
  attribute syn_preserve of IO, IOB : signal is true;
end entity IOBUFDS_FDCE_LVDS;

architecture lvds_buff0 of IOBUFDS_FDCE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  iff_p : FDCE port map (D => i_p, CE => CE, C => C, CLR => CLR, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_F