div3.vhd

用VHDL硬件描述语言实现的良好运行的三分频电路

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div3 is
   Port(clk : in std_logic;
		resetp : in std_logic;
        clkout : out std_logic);
end div3;

architecture div3behav of div3 is
signal counta,countb:std_logic_vector(2 downto 0);
signal clka,clkb:std_logic;
begin


count1:process (clk,resetp)
begin
	if resetp = '1' then   -------------reset pulse
   		counta <="000";
  		clka <= '0' ;
	elsif(clk'event and clk='1') then  ------------- generate clka
  		if counta =2 then
     		counta <="000";
			clka <= NOT clka;
		elsif counta = 1 then
   			clka <= NOT clka;
			counta <= counta + 1;
		else	 
			counta <= counta + 1;
		end if;
   	end if;
end process count1;

count2:process (clk,resetp)
begin
	if resetp = '1' then   -------------reset pulse
    	countb<="000";
  		clkb<= '0' ;
	elsif(clk'event and clk='0') then  ------------generate clkb
   		if countb =2 then
     		countb <="000";
			clkb<= NOT clkb;
		elsif countb = 1 then
  			clkb <= NOT clkb;
			countb <= countb + 1;
   		else	 
			countb <= countb + 1;
		end if;
  	end if;
	 	 
 end process count2;
clkout <= clka or clkb ;  --------generate clkout 
end div3behav;