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一个实现简单的数字锁相环Verilog代码

# Reading D:/Modeltech_6.3a/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.3a Jun 25 2007 
# //
# //  Copyright 1991-2007 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# OpenFile E:/Work/dpll_20071023/DPLL.mpf 
# Loading project DPLL
# reading D:\Modeltech_6.3a\win32/../modelsim.ini
# Loading project dds
# Compile of dds_tb.v was successful.
# Compile of dds.v was successful.
# Compile of rom_syn.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim -L D:/Modeltech_6.3a/altera_basic -gui -novopt work.dds_tb
# vsim -L D:/Modeltech_6.3a/altera_basic -gui -novopt work.dds_tb 
# Refreshing E:\Work\dds_20071031\work.dds_tb
# Loading work.dds_tb
# Refreshing E:\Work\dds_20071031\work.dds
# Loading work.dds
# Refreshing E:\Work\dds_20071031\work.rom
# Loading work.rom
# ** Warning: (vsim-3010) [TSCALE] - Module 'rom' has a `timescale directive in effect, but previous modules do not.
#         Region: /dds_tb/dds/rom
# Refreshing E:\Work\dds_20071031\work.rom_altsyncram
# Loading work.rom_altsyncram
# Loading D:/Modeltech_6.3a/altera_basic.cycloneii_ram_block
# Loading D:/Modeltech_6.3a/altera_basic.cycloneii_ram_register
# Loading D:/Modeltech_6.3a/altera_basic.cycloneii_ram_pulse_generator
# Compile of dds_tb.v was successful.
# Compile of dds.v was successful.
# Compile of rom_syn.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing E:\Work\dds_20071031\work.dds_tb
# Loading work.dds_tb
# Refreshing E:\Work\dds_20071031\work.dds
# Loading work.dds
# Refreshing E:\Work\dds_20071031\work.rom
# Loading work.rom
# ** Warning: (vsim-3010) [TSCALE] - Module 'rom' has a `timescale directive in effect, but previous modules do not.
#         Region: /dds_tb/dds/rom
# Refreshing E:\Work\dds_20071031\work.rom_altsyncram
# Loading work.rom_altsyncram
do wave.do
run 50us
# Break key hit 
# Break in Module cycloneii_ram_register at D:/Altera/quartus/eda/sim_lib/cycloneii_atoms.v line 474