voptv98xzi

来自「一个实现简单的数字锁相环Verilog代码」· 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity FFD is
    port(
        clock           : in     vl_logic;
        reset           : in     vl_logic;
        D               : in     vl_logic;
        Q               : out    vl_logic;
        Q_not           : out    vl_logic
    );
end FFD;