jk.v

来自「一个实现简单的数字锁相环Verilog代码」· Verilog 代码 · 共 21 行

module JK(clock,
			 reset,
			 J,K,
			 Q,Q_not
			 );
input  clock,
		 reset,
		 J,K;
output Q,Q_not;

reg Q;

always @(posedge clock or negedge reset)
if(~reset)
   Q <= 0;
else
   Q <= (J&(~Q))|((~K)&Q);

assign Q_not = ~Q;

endmodule