dds.tlg

FPGA中实现基于查找表方式（LUT）的DDS实现

Selecting top level module dds
@N: CG364 :"D:\Work\dds_20071031\dds.v":1:7:1:9|Synthesizing module dds

@W: CL106 :"D:\Work\dds_20071031\dds.v":18:0:18:5|Register addr_acc with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.