dds.srr

FPGA中实现基于查找表方式（LUT）的DDS实现

#Build: Synplify Pro 8.6.2, Build 013R, Jun  5 2006
#install: C:\Program Files\Synplicity\fpga_862
#OS: Windows XP 5.1
#Hostname: DONNYLU

#Wed Oct 31 14:45:37 2007

$ Start of Compile
#Wed Oct 31 14:45:37 2007

Synplicity Verilog Compiler, version 3.6t, Build 206R, built Aug  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"C:\Program Files\Synplicity\fpga_862\lib\proasic\proasic.v"
@I::"D:\Work\dds_20071031\dds.v"
Verilog syntax check successful!
Selecting top level module dds
@N: CG364 :"D:\Work\dds_20071031\dds.v":1:7:1:9|Synthesizing module dds

@W: CL106 :"D:\Work\dds_20071031\dds.v":18:0:18:5|Register addr_acc with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 31 14:45:37 2007

###########################################################]
###########################################################[
Synplicity Proasic Technology Mapper, Version 8.6.2, Build 027R, Built Aug 11 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.6.2
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 21MB peak: 22MB)
@N: MF176 |Default generator successful 

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 21MB peak: 23MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)
Promoting Net clk_c on GL33  clk_pad
Buffering reset_c, fanout 20 segments 2

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Added 1 Buffers
Added 0 Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)
@N: BN191 |Writing property annotation file D:\Work\dds_20071031\rev_1\dds.tap.
Writing Analyst data base D:\Work\dds_20071031\rev_1\dds.srm
@N: BN225 |Writing default property annotation file D:\Work\dds_20071031\rev_1\dds.map.
Writing EDIF Netlist and constraint files
Found clock dds|clk with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Oct 31 14:45:39 2007
#


Top view:               dds
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 979.989

                   Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------
dds|clk            1.0 MHz       50.0 MHz      1000.000      20.011        979.989     inferred     Inferred_clkgroup_0
=======================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------
dds|clk   dds|clk  |  1000.000    979.989  |  No paths    -      |  No paths    -      |  No paths    -    
===========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: dds|clk
====================================



Starting Points with Worst Slack
********************************

                Starting                                             Arrival            
Instance        Reference     Type     Pin     Net                   Time        Slack  
                Clock                                                                   
----------------------------------------------------------------------------------------
addr_acc[0]     dds|clk       DFFB     Q       addr_acc[0]           0.260       979.989
addr_acc[1]     dds|clk       DFFB     Q       addr_acc[1]           0.260       980.689
addr_acc[2]     dds|clk       DFFB     Q       addr_acc[2]           0.260       982.515
addr_acc[3]     dds|clk       DFFB     Q       addr_acc_i_0_i[3]     0.260       984.277
addr_acc[4]     dds|clk       DFFB     Q       addr_acc[4]           0.260       986.167
addr_acc[5]     dds|clk       DFFB     Q       addr_acc[5]           0.260       988.525