sap.log

来自「FPGA中实现基于查找表方式（LUT）的DDS实现」· LOG 代码 · 共 14 行

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Synplicity Proasic Technology Mapper, Version 8.6.2, Build 027R, Built Aug 11 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.6.2
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


@N: BN225 |Writing default property annotation file D:\Work\dds_20071031\rev_1\dds.sap.
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 31 14:45:38 2007

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