dds.v

来自「FPGA中实现基于查找表方式（LUT）的DDS实现」· Verilog 代码 · 共 37 行

module dds(clk,
           reset,
           k,
           initial_phase,
		     data_out
           );
input   clk,
        reset;
input[9:0]  k,
		      initial_phase;
output[7:0] data_out;

// Address accumulator
reg [9:0]   addr_acc;
wire[7:0]	  rom_data;
wire[7:0]   rom_addr;						// Length of a sine data in a period is 10 bit, 
																// but the length of ROM is 8 bit because 
																// it only need to store previous 1/4 of a period
																																								
always @(posedge clk or negedge reset)
if(~reset)
	addr_acc <= initial_phase;
else
	addr_acc <= addr_acc+k;
	
// Address and data convertor of rom
assign rom_addr = (addr_acc[8])?(~addr_acc[7:0]):(addr_acc[7:0]);		// When Address in [pi/2,pi],[pi*3/2,pi*2], convert address to ROM
assign data_out = (addr_acc[9])?({~rom_data[7:0]+1}):(rom_data);    // When Address in [0,pi/2], [pi,pi*3/2], convert the polar of data from ROM
																																		// This method only for sine wave		

rom rom(.clock(clk),
        .aclr(~reset),
        .address(rom_addr),
        .q(rom_data)
        );
	
endmodule