dds_tb.v

来自「FPGA中实现基于查找表方式（LUT）的DDS实现」· Verilog 代码 · 共 26 行

module dds_tb;
reg	clk,
		reset;
reg [9:0]	k,
					initial_phase;
wire[7:0]	data_out;		

dds dds(.clk(clk),
				.reset(reset),
				.k(k),
				.initial_phase(initial_phase),
				.data_out(data_out)
				);

initial begin
	clk = 0;
	k = 1;
	initial_phase = 0;
	reset = 1;
	#10 reset = 0;
	#25	reset = 1;
end

always #10 clk = ~clk;   // sys_clock

endmodule