acexep1k10tc100.tan.qmsg

喷绘机编程!

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter\[0\] register led1\[4\] 48.78 MHz 20.5 ns Internal " "Info: Clock \"clk\" has Internal fmax of 48.78 MHz between source register \"counter\[0\]\" and destination register \"led1\[4\]\" (period= 20.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.400 ns + Longest register register " "Info: + Longest register to register delay is 19.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LC5_C2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C2; Fanout = 3; REG Node = 'counter\[0\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "" { counter[0] } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.700 ns) 1.000 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC5_C2 2 " "Info: 2: + IC(0.300 ns) + CELL(0.700 ns) = 1.000 ns; Loc. = LC5_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "1.000 ns" { counter[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.200 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC6_C2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.200 ns; Loc. = LC6_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.400 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC7_C2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 1.400 ns; Loc. = LC7_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.600 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC8_C2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 1.600 ns; Loc. = LC8_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 2.300 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC1_C4 2 " "Info: 6: + IC(0.500 ns) + CELL(0.200 ns) = 2.300 ns; Loc. = LC1_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.700 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.500 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC2_C4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 2.500 ns; Loc. = LC2_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.700 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC3_C4 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 2.700 ns; Loc. = LC3_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.900 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 9 COMB LC4_C4 2 " "Info: 9: + IC(0.000 ns) + CELL(0.200 ns) = 2.900 ns; Loc. = LC4_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.100 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 10 COMB LC5_C4 2 " "Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 3.100 ns; Loc. = LC5_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.300 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 11 COMB LC6_C4 2 " "Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 3.300 ns; Loc. = LC6_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.500 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 12 COMB LC7_C4 2 " "Info: 12: + IC(0.000 ns) + CELL(0.200 ns) = 3.500 ns; Loc. = LC7_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.700 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 13 COMB LC8_C4 2 " "Info: 13: + IC(0.000 ns) + CELL(0.200 ns) = 3.700 ns; Loc. = LC8_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 4.400 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 14 COMB LC1_C6 2 " "Info: 14: + IC(0.500 ns) + CELL(0.200 ns) = 4.400 ns; Loc. = LC1_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.700 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.600 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 15 COMB LC2_C6 2 " "Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 4.600 ns; Loc. = LC2_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.800 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 16 COMB LC3_C6 2 " "Info: 16: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = LC3_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\] 17 COMB LC4_C6 2 " "Info: 17: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = LC4_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.200 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\] 18 COMB LC5_C6 2 " "Info: 18: + IC(0.000 ns) + CELL(0.200 ns) = 5.200 ns; Loc. = LC5_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.400 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\] 19 COMB LC6_C6 2 " "Info: 19: + IC(0.000 ns) + CELL(0.200 ns) = 5.400 ns; Loc. = LC6_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[17] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.600 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\] 20 COMB LC7_C6 2 " "Info: 20: + IC(0.000 ns) + CELL(0.200 ns) = 5.600 ns; Loc. = LC7_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[18] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.800 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\] 21 COMB LC8_C6 2 " "Info: 21: + IC(0.000 ns) + CELL(0.200 ns) = 5.800 ns; Loc. = LC8_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[19] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 6.500 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\] 22 COMB LC1_C8 2 " "Info: 22: + IC(0.500 ns) + CELL(0.200 ns) = 6.500 ns; Loc. = LC1_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.700 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[20] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.700 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\] 23 COMB LC2_C8 2 " "Info: 23: + IC(0.000 ns) + CELL(0.200 ns) = 6.700 ns; Loc. = LC2_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[21] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.900 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\] 24 COMB LC3_C8 2 " "Info: 24: + IC(0.000 ns) + CELL(0.200 ns) = 6.900 ns; Loc. = LC3_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[22] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 8.300 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[23\] 25 COMB LC4_C8 2 " "Info: 25: + IC(0.000 ns) + CELL(1.400 ns) = 8.300 ns; Loc. = LC4_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[23\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "1.400 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 10.200 ns reduce_nor~237 26 COMB LC6_C8 1 " "Info: 26: + IC(0.300 ns) + CELL(1.600 ns) = 10.200 ns; Loc. = LC6_C8; Fanout = 1; COMB Node = 'reduce_nor~237'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "1.900 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] reduce_nor~237 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 12.600 ns reduce_nor~241 27 COMB LC7_C7 1 " "Info: 27: + IC(1.000 ns) + CELL(1.400 ns) = 12.600 ns; Loc. = LC7_C7; Fanout = 1; COMB Node = 'reduce_nor~241'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { reduce_nor~237 reduce_nor~241 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 14.300 ns reduce_nor~0 28 COMB LC1_C7 9 " "Info: 28: + IC(0.300 ns) + CELL(1.400 ns) = 14.300 ns; Loc. = LC1_C7; Fanout = 9; COMB Node = 'reduce_nor~0'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "1.700 ns" { reduce_nor~241 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.400 ns) 17.400 ns led1\[0\]~74 29 COMB LC5_C20 7 " "Info: 29: + IC(1.700 ns) + CELL(1.400 ns) = 17.400 ns; Loc. = LC5_C20; Fanout = 7; COMB Node = 'led1\[0\]~74'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "3.100 ns" { reduce_nor~0 led1[0]~74 } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.000 ns) 19.400 ns led1\[4\] 30 REG LC2_C21 4 " "Info: 30: + IC(1.000 ns) + CELL(1.000 ns) = 19.400 ns; Loc. = LC2_C21; Fanout = 4; REG Node = 'led1\[4\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.000 ns" { led1[0]~74 led1[4] } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.300 ns 68.56 % " "Info: Total cell delay = 13.300 ns ( 68.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 31.44 % " "Info: Total interconnect delay = 6.100 ns ( 31.44 % )" {  } {  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "19.400 ns" { counter[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] reduce_nor~237 reduce_nor~241 reduce_nor~0 led1[0]~74 led1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "19.400 ns" { counter[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] reduce_nor~237 reduce_nor~241 reduce_nor~0 led1[0]~74 led1[4] } { 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.300ns 1.000ns 0.300ns 1.700ns 1.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.400ns 1.600ns 1.400ns 1.400ns 1.400ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'clk'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "" { clk } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns led1\[4\] 2 REG LC2_C21 4 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C21; Fanout = 4; REG Node = 'led1\[4\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.400 ns" { clk led1[4] } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk led1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out led1[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'clk'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "" { clk } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns counter\[0\] 2 REG LC5_C2 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_C2; Fanout = 3; REG Node = 'counter\[0\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.400 ns" { clk counter[0] } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out counter[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk led1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out led1[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out counter[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 8 -1 0 } }  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "19.400 ns" { counter[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] reduce_nor~237 reduce_nor~241 reduce_nor~0 led1[0]~74 led1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "19.400 ns" { counter[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] reduce_nor~237 reduce_nor~241 reduce_nor~0 led1[0]~74 led1[4] } { 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.300ns 1.000ns 0.300ns 1.700ns 1.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.400ns 1.600ns 1.400ns 1.400ns 1.400ns 1.000ns } } } { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk led1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out led1[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out counter[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk ledout\[1\] led1\[1\] 10.900 ns register " "Info: tco from clock \"clk\" to destination pin \"ledout\[1\]\" through register \"led1\[1\]\" is 10.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 32 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'clk'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "" { clk } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns led1\[1\] 2 REG LC7_C20 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_C20; Fanout = 3; REG Node = 'led1\[1\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "0.400 ns" { clk led1[1] } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk led1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out led1[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register pin " "Info: + Longest register to pin delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led1\[1\] 1 REG LC7_C20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C20; Fanout = 3; REG Node = 'led1\[1\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "" { led1[1] } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(6.300 ns) 8.000 ns ledout\[1\] 2 PIN PIN_16 0 " "Info: 2: + IC(1.700 ns) + CELL(6.300 ns) = 8.000 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'ledout\[1\]'" {  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "8.000 ns" { led1[1] ledout[1] } "NODE_NAME" } "" } } { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 78.75 % " "Info: Total cell delay = 6.300 ns ( 78.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 21.25 % " "Info: Total interconnect delay = 1.700 ns ( 21.25 % )" {  } {  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "8.000 ns" { led1[1] ledout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "8.000 ns" { led1[1] ledout[1] } { 0.000ns 1.700ns } { 0.000ns 6.300ns } } }  } 0}  } { { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "2.400 ns" { clk led1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out led1[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" "" { Report "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100_cmp.qrpt" Compiler "ACEXep1k10tc100" "UNKNOWN" "V1" "D:/FPGAtest/ACEXep1k10tc100/db/ACEXep1k10tc100.quartus_db" { Floorplan "D:/FPGAtest/ACEXep1k10tc100/" "" "8.000 ns" { led1[1] ledout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "8.000 ns" { led1[1] ledout[1] } { 0.000ns 1.700ns } { 0.000ns 6.300ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 07 20:11:23 2008 " "Info: Processing ended: Mon Jan 07 20:11:23 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}