acexep1k10tc100.map.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 07 20:11:13 2008 " "Info: Processing started: Mon Jan 07 20:11:13 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ACEXep1k10tc100 -c ACEXep1k10tc100 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ACEXep1k10tc100 -c ACEXep1k10tc100" {  } {  } 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "7 ACEXep1k10tc100.v(12) " "Warning: (10229) Verilog HDL Expression warning at ACEXep1k10tc100.v(12): truncated literal to match 7 bits" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 12 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ACEXep1k10tc100.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ACEXep1k10tc100.v" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "led " "Info: Elaborating entity \"led\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "ACEXep1k10tc100.v(13) " "Warning: Verilog HDL unsupported feature warning at ACEXep1k10tc100.v(13): Initial Construct is not supported and will be ignored" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 ACEXep1k10tc100.v(17) " "Warning: Verilog HDL assignment warning at ACEXep1k10tc100.v(17): truncated value with size 32 to match size of target (25)" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 ACEXep1k10tc100.v(20) " "Warning: Verilog HDL assignment warning at ACEXep1k10tc100.v(20): truncated value with size 32 to match size of target (25)" {  } { { "ACEXep1k10tc100.v" "" { Text "D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.v" 20 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus501/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus501/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus501/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus501/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "66 " "Info: Implemented 66 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 07 20:11:15 2008 " "Info: Processing ended: Mon Jan 07 20:11:15 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}