acexep1k10tc100.map.rpt

喷绘机编程!

+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 66      ;
; Total combinational functions     ; 45      ;
;     -- Total 4-input functions    ; 9       ;
;     -- Total 3-input functions    ; 2       ;
;     -- Total 2-input functions    ; 8       ;
;     -- Total 1-input functions    ; 26      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 32      ;
; Total logic cells in carry chains ; 25      ;
; I/O pins                          ; 8       ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 32      ;
; Total fan-out                     ; 175     ;
; Average fan-out                   ; 2.36    ;
+-----------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                             ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                              ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; |led                               ; 66 (42)     ; 32           ; 0           ; 8    ; 34 (10)      ; 21 (21)           ; 11 (11)          ; 25 (1)          ; |led                                                             ;
;    |lpm_add_sub:add_rtl_0|         ; 24 (0)      ; 0            ; 0           ; 0    ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |led|lpm_add_sub:add_rtl_0                                       ;
;       |addcore:adder|              ; 24 (1)      ; 0            ; 0           ; 0    ; 24 (1)       ; 0 (0)             ; 0 (0)            ; 24 (1)          ; |led|lpm_add_sub:add_rtl_0|addcore:adder                         ;
;          |a_csnbuffer:result_node| ; 23 (23)     ; 0            ; 0           ; 0    ; 23 (23)      ; 0 (0)             ; 0 (0)            ; 23 (23)         ; |led|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 32    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 7     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 25          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_7nh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Jan 07 20:11:13 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ACEXep1k10tc100 -c ACEXep1k10tc100
Warning: (10229) Verilog HDL Expression warning at ACEXep1k10tc100.v(12): truncated literal to match 7 bits
Info: Found 1 design units, including 1 entities, in source file ACEXep1k10tc100.v
    Info: Found entity 1: led
Info: Elaborating entity "led" for the top level hierarchy
Warning: Verilog HDL unsupported feature warning at ACEXep1k10tc100.v(13): Initial Construct is not supported and will be ignored
Warning: Verilog HDL assignment warning at ACEXep1k10tc100.v(17): truncated value with size 32 to match size of target (25)
Warning: Verilog HDL assignment warning at ACEXep1k10tc100.v(20): truncated value with size 32 to match size of target (25)
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus501/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Implemented 74 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 7 output pins
    Info: Implemented 66 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Mon Jan 07 20:11:15 2008
    Info: Elapsed time: 00:00:02