acexep1k10tc100.v

来自「喷绘机编程!」· Verilog 代码 · 共 29 行

module led(clk,ledout);

input clk;
output [6:0] ledout;
wire clk;
wire [6:0] ledout;
reg [24:0] counter;
reg [6:0] led1;

initial
begin
   led1=7'b11111110;
end

always @ (posedge clk)
begin
  counter=counter+1;
  if(counter==5000000)
   begin
    counter=0;
    led1=~(~led1<<1);
    if(led1==7'b0111111)
     led1=7'b1111110;
   end
end

assign ledout=led1;

endmodule