rs232.vhd

串行通信实验

    begin
        if RST = '1' then
            baud_rate <= '0';
            cnt_BDR <= "0000";
        elsif rising_edge(CLK_IN) then
            baud_rate <= '0';
            if BDRx16 = '1' then
                cnt_BDR <= cnt_BDR + 1;
                if cnt_BDR = "1111" then
                    baud_rate <= '1';
                end if;
            else
                cnt_BDR <= cnt_BDR;
            end if;
        end if;
    end process tx_baud_rate_gen;
    ------------------------------------------------------------------------------------
    --
    --A 16 times baud rate used for sampling.
    --
    baud_rate16_gen: process(CLK_IN, RST)
    begin
        if RST = '1' then
            BDRx16 <= '0';
            cnt_BDRx16 <= "00000000";
        elsif rising_edge(CLK_IN) then
            BDRx16 <= '0';
            if cnt_BDRx16 = "10100010" then
                cnt_BDRx16 <= "00000000";
                BDRx16 <= '1';
            else
                cnt_BDRx16 <= cnt_BDRx16 + 1;
            end if;
        end if;
    end process baud_rate16_gen;    
    --
    ------------------------------------------------------------------------------------
    --
    --The transmiting finite state machine.
    --
    tx_fsm: process(RST, CLK_IN)
        begin
            if RST = '1' then
                tx_busy <= '0';
                TXD <= '1';
                tx_data <= (others => '0');
                tx_reg <= (others => '1');
                tx_bit_cnt <= (others => '0');
                tx_st <= tx_idle;
            elsif rising_edge(CLK_IN) then
                tx_busy <= '0';
					 if tx_busy = '0' then
                    tx_data <= kbd_data;
					 end if;
					 if tx_data = kbd_data then--Judging if the received data 
					     PS2_data_vir <= '0';--has been changed.
					 else
						  PS2_data_vir <= '1';
					 end if;
                --
                case tx_st is
                    when tx_idle =>
                        if PS2_data_vir = '1' then
                            temp_data <= tx_data;--Load the data into TXD register.
                            tx_busy <= '1';
                            tx_st <= tx_start;
                        else
                            tx_st <= tx_idle;
                        end if;
                    when tx_start =>
                        if baud_rate = '1' then
                            tx_st <= tx_shifting;
                            tx_reg <= '1' & temp_data & '0';--Composing the frame.
                        end if;
                    when tx_shifting => 
                        if baud_rate = '1' then
                            TXD <= tx_reg(0);
                            tx_bit_cnt <= tx_bit_cnt + 1;
                            tx_reg <= '1' & tx_reg(9 downto 1);--Right shift.
                            if tx_bit_cnt = "1000" then
                                tx_st <= tx_stop;
                            end if;
                        end if;
                    when tx_stop =>
                        if baud_rate = '1' then
                            tx_bit_cnt <= (others => '0');
									 tx_reg <= (others => '1');
									 TXD <= '1';--When idle, TXD must be active(high).
                            tx_st <= tx_idle;
                        end if;
                    when others =>
                        tx_st <= tx_idle;
                end case;
            end if;
        end process tx_fsm;
    
    --------------------------------------------------------------------------------------
    --
    --Generating the RX sampling clock.
    --
    rx_smpl_rate_gen: process(RST, CLK_IN)
        begin 
            if RST = '1' then
                rx_smpl_rate <= '0';
                rx_div <= (others => '0');
            elsif rising_edge(CLK_IN) then
                rx_smpl_rate <= '0';
                if rx_sync = '1' then
                    rx_div <= (others => '0');
                elsif BDRx16 = '1' then
                    if rx_div = "111" then--Notice that the sampling
                        rx_div <= "000";--point is in the mid of the data bit.
                        rx_smpl_rate <= '1';
                    else
                        rx_div <= rx_div + 1;
                    end if;
                end if;
            end if;
        end process rx_smpl_rate_gen;
    ------------------------------------------------------------------------------------
    --
    --RXD finite state machine.
    --
    rx_fsm: process(RST, CLK_IN)
        begin
            if RST = '1' then
                rx_reg <= (others => '0');
                rx_data <= (others => '0');
                rx_bit_cnt <= (others => '0');
                rx_sync <= '0';
                rx_err_ind <= '0';--For error indication, did not used.
                rx_data_rdy <= '0';
                rx_st <= rx_idle;
            elsif rising_edge(CLK_IN) then
                rx_sync <= '0';
                if rx_data_rdy = '1' then
                    rx_err_ind <= '0';
                    rx_data_rdy <= '0';
                end if;
                -----
                case rx_st is
                    when rx_idle => 
                        rx_bit_cnt <= (others => '0');
                        if BDRx16 = '1' then
                            if RXD = '0' then--Looks like a start bit. 
                                rx_st <= rx_start;
                                rx_sync <= '1';--Synchronizing the smapling clock.
                            end if;
                        end if;
                    when rx_start => 
                        if rx_smpl_rate = '1' then
                            if RXD = '1' then--Frame error.
                                rx_st <= rx_err;
                            else
                                rx_st <= rx_null;
                            end if;
                        end if;
                    when rx_null => --In order to sample the value in the mid of
                        if rx_smpl_rate = '1' then--the data bit, a NULL state 
                            if rx_bit_cnt >= 9 then--setted for synchronizing.
                                rx_st <= rx_stop;
                            else
                                rx_st <= rx_shifting;
                            end if;
                        end if;
                    when rx_shifting =>
                        if rx_smpl_rate = '1' then
                            rx_bit_cnt <= rx_bit_cnt + 1;
                            rx_reg <= RXD & rx_reg(8 downto 1);
                            rx_st <= rx_null;
                        end if;
                    when rx_stop =>
                        if rx_smpl_rate = '1' then
                            rx_data <= rx_reg(7 downto 0);
                            rx_data_rdy <= '1';
                            rx_st <= rx_idle;
									 rx_bit_cnt <= (others => '0');
                        end if;
                    when rx_err =>
                        rx_err_ind <= '1';
                        if RXD = '1' then
                            rx_st <= rx_idle;
                        end if;
                end case;
            end if;
        end process rx_fsm;
    
    --///********************************************************************////
    ------------------------------------------------------------------------------------
    --
    process(RST, CLK_IN)
        begin
            if RST = '1' then
                key_code <= (others => '0');
            elsif rising_edge(CLK_IN) then
					 key_code <= decoding(kbd_data(7 downto 0));--Data from the keyboard.
					 rx_code <= decoding(rx_data(7 downto 0));--Data from the RS232 port.
            end if;
        end process;
    ------------------------------------------------------------------------------------
    --
    --Displaying the character on the LCD.
    --Only the character "A" to "Z" can be displayed.
    --
    LCD_displaying: process(clk)
    begin
        if rising_edge(clk) then
            cnt1 <= cnt1 + 1;     
            s_sf_ce0 <= '1';--A constant, StrataFlash disabled. 
                            --Full read/write access to LCD.
            --
            if init_over = '0' then    
                case(cnt1(18 downto 15)) is
                    when x"0" => lcd_data <= "000011";--Write SF_D<11:8>=0x3.
                    when x"1" => lcd_data <= "000011";--Write SF_D<11:8>=0x3.
                    when x"2" => lcd_data <= "000011";--Write SF_D<11:8>=0x3.
                    when x"3" => lcd_data <= "000010";--Write SF_D<11:8>=0x2.
                    when x"4" => lcd_data <= "000010";--Write SF_D<11:8>=0x2. 
                    when x"5" => lcd_data <= "001000";--Write SF_D<11:8>=0x8.
                    when x"6" => lcd_data <= "000000";--Write SF_D<11:8>=0x0.
                    when x"7" => lcd_data <= "000110";--Write SF_D<11:8>=0x6.
                    when x"8" => lcd_data <= "000000";--Write SF_D<11:8>=0x0.
                    when x"9" => lcd_data <= "001100";--Write SF_D<11:8>=0xC.
                    when x"A" => lcd_data <= "000000";--Write SF_D<11:8>=0x0.
                    when x"B" => lcd_data <= "000001";--Write SF_D<11:8>=0x1.
                    when x"C" => lcd_data <= "001000";--Start display at
                    when x"D" => lcd_data <= "000111";--address 0x7.(Useless)
                    when x"E" => init_over <= '1';
					     --
					     --Initializing finished.
					     --
                    when others   => lcd_data <= "010000";--Disable the LCD writing.
                end case;
                lcd_enable <= cnt1(14);
            else
                case cnt1(7 downto 6) is
                    --
                    --start to display the corresponding character.
                    --
                    when "00" => lcd_data <= "10" & key_code(7 downto 4);
                    when "01" => lcd_data <= "10" & key_code(3 downto 0);
                    when "10" => lcd_data <= "10" & rx_code(7 downto 4);
                    when "11" => lcd_data <= "10" & rx_code(3 downto 0);
                    when others => lcd_data <= "000000";
                end case;
                lcd_enable <= cnt1(5);
            end if;               
        end if;
    end process LCD_displaying;
    ---------------------------------------------------------------------------------
    --
	 --Now specify the interface between the FPGA and the LCD.
	 --
    LCD_RS <= lcd_data(5);
    LCD_RW <= lcd_data(4);
    SF_D(11)  <= lcd_data(3);
    SF_D(10) <= lcd_data(2);
    SF_D(9) <= lcd_data(1);
    SF_D(8) <= lcd_data(0);
    LCD_EN <= lcd_enable;
    SF_CE0 <= s_sf_ce0;
--------------------------------------------------------------------------------------
end Behavior;
--
--The end of the file;
--
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