📄 code_tran.rpt
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Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\code_tran.rpt
code_tran
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\code_tran.rpt
code_tran
** EQUATIONS **
clk : INPUT;
scan_cnt0 : INPUT;
scan_cnt1 : INPUT;
scan_cnt2 : INPUT;
scan_cnt3 : INPUT;
-- Node name is 'butt_code0'
-- Equation name is 'butt_code0', type is output
butt_code0 = _LC8_A10;
-- Node name is 'butt_code1'
-- Equation name is 'butt_code1', type is output
butt_code1 = _LC6_A10;
-- Node name is 'butt_code2'
-- Equation name is 'butt_code2', type is output
butt_code2 = _LC1_A9;
-- Node name is 'butt_code3'
-- Equation name is 'butt_code3', type is output
butt_code3 = _LC3_A9;
-- Node name is ':6'
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = scan_cnt0 & scan_cnt1
# scan_cnt1 & scan_cnt3
# !scan_cnt0 & scan_cnt2 & scan_cnt3
# scan_cnt0 & !scan_cnt2 & scan_cnt3;
-- Node name is ':8'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = scan_cnt0 & scan_cnt1
# scan_cnt2 & !scan_cnt3
# !scan_cnt0 & !scan_cnt1 & !scan_cnt2 & scan_cnt3;
-- Node name is ':10'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_A10 & !_LC4_A10
# !_LC1_A10 & !_LC2_A12 & _LC5_A10;
-- Node name is ':12'
-- Equation name is '_LC8_A10', type is buried
_LC8_A10 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_A10
# !_LC2_A9 & _LC2_A10
# !_LC2_A9 & _LC3_A10;
-- Node name is ':283'
-- Equation name is '_LC4_A12', type is buried
!_LC4_A12 = _LC4_A12~NOT;
_LC4_A12~NOT = LCELL( _EQ005);
_EQ005 = !scan_cnt3
# scan_cnt2
# scan_cnt1
# !scan_cnt0;
-- Node name is ':319'
-- Equation name is '_LC6_A9', type is buried
!_LC6_A9 = _LC6_A9~NOT;
_LC6_A9~NOT = LCELL( _EQ006);
_EQ006 = scan_cnt3
# !scan_cnt2
# !scan_cnt1
# scan_cnt0;
-- Node name is ':331'
-- Equation name is '_LC7_A9', type is buried
_LC7_A9 = LCELL( _EQ007);
_EQ007 = scan_cnt0 & !scan_cnt1 & scan_cnt2 & !scan_cnt3;
-- Node name is ':343'
-- Equation name is '_LC5_A9', type is buried
!_LC5_A9 = _LC5_A9~NOT;
_LC5_A9~NOT = LCELL( _EQ008);
_EQ008 = scan_cnt1
# scan_cnt0
# scan_cnt3
# !scan_cnt2;
-- Node name is ':355'
-- Equation name is '_LC2_A12', type is buried
!_LC2_A12 = _LC2_A12~NOT;
_LC2_A12~NOT = LCELL( _EQ009);
_EQ009 = !scan_cnt1
# !scan_cnt0
# scan_cnt2
# scan_cnt3;
-- Node name is ':367'
-- Equation name is '_LC2_A10', type is buried
_LC2_A10 = LCELL( _EQ010);
_EQ010 = !scan_cnt0 & scan_cnt1 & !scan_cnt2 & !scan_cnt3;
-- Node name is ':379'
-- Equation name is '_LC2_A9', type is buried
!_LC2_A9 = _LC2_A9~NOT;
_LC2_A9~NOT = LCELL( _EQ011);
_EQ011 = scan_cnt1
# !scan_cnt0
# scan_cnt3
# scan_cnt2;
-- Node name is ':391'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ012);
_EQ012 = !scan_cnt0 & !scan_cnt1 & !scan_cnt2 & !scan_cnt3;
-- Node name is '~396~1'
-- Equation name is '~396~1', location is LC4_A10, type is buried.
-- synthesized logic cell
!_LC4_A10 = _LC4_A10~NOT;
_LC4_A10~NOT = LCELL( _EQ013);
_EQ013 = _LC2_A9
# _LC2_A10;
-- Node name is ':474'
-- Equation name is '_LC4_A9', type is buried
_LC4_A9 = LCELL( _EQ014);
_EQ014 = !scan_cnt0 & !scan_cnt1
# !scan_cnt0 & scan_cnt2
# !scan_cnt2 & !scan_cnt3
# !scan_cnt1 & !scan_cnt3
# !scan_cnt0 & !scan_cnt3
# scan_cnt0 & scan_cnt1 & scan_cnt3
# scan_cnt0 & scan_cnt1 & !scan_cnt2
# scan_cnt1 & scan_cnt2 & scan_cnt3;
-- Node name is '~486~1'
-- Equation name is '~486~1', location is LC5_A10, type is buried.
-- synthesized logic cell
_LC5_A10 = LCELL( _EQ015);
_EQ015 = _LC4_A9 & !_LC5_A9 & !_LC7_A9
# !_LC5_A9 & _LC6_A9 & !_LC7_A9;
-- Node name is ':508'
-- Equation name is '_LC8_A9', type is buried
_LC8_A9 = LCELL( _EQ016);
_EQ016 = !scan_cnt3
# scan_cnt1 & scan_cnt2
# !scan_cnt1 & !scan_cnt2
# !scan_cnt0 & scan_cnt1
# !scan_cnt0 & !scan_cnt2;
-- Node name is '~517~1'
-- Equation name is '~517~1', location is LC3_A12, type is buried.
-- synthesized logic cell
_LC3_A12 = LCELL( _EQ017);
_EQ017 = !scan_cnt0 & !scan_cnt1 & !scan_cnt2 & scan_cnt3
# scan_cnt0 & scan_cnt1 & scan_cnt2 & !scan_cnt3;
-- Node name is ':525'
-- Equation name is '_LC1_A12', type is buried
_LC1_A12 = LCELL( _EQ018);
_EQ018 = _LC3_A12 & !_LC6_A9
# !_LC4_A12 & !_LC6_A9 & _LC8_A9;
-- Node name is ':534'
-- Equation name is '_LC3_A10', type is buried
_LC3_A10 = LCELL( _EQ019);
_EQ019 = !_LC2_A12 & !_LC5_A9 & _LC7_A9
# _LC1_A12 & !_LC2_A12 & !_LC5_A9;
Project Information d:\my work\fpga\13_1908\vhdlcoder\code_tran.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,405K
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