📄 traffic_mux.rpt
字号:
- 5 - A 21 DFFE + 2 0 1 0 :19
- 1 - A 21 DFFE + 3 0 1 0 :21
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic_mux.rpt
traffic_mux
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic_mux.rpt
traffic_mux
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic_mux.rpt
traffic_mux
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 reset
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic_mux.rpt
traffic_mux
** EQUATIONS **
clk : INPUT;
ena_scan : INPUT;
recount : INPUT;
reset : INPUT;
sign_state0 : INPUT;
-- Node name is 'load0'
-- Equation name is 'load0', type is output
load0 = _LC1_A21;
-- Node name is 'load1'
-- Equation name is 'load1', type is output
load1 = _LC5_A21;
-- Node name is 'load2'
-- Equation name is 'load2', type is output
load2 = _LC3_A21;
-- Node name is 'load3'
-- Equation name is 'load3', type is output
load3 = _LC4_A21;
-- Node name is 'load4'
-- Equation name is 'load4', type is output
load4 = _LC8_A21;
-- Node name is 'load5'
-- Equation name is 'load5', type is output
load5 = _LC6_A21;
-- Node name is 'load6'
-- Equation name is 'load6', type is output
load6 = _LC2_A21;
-- Node name is 'load7'
-- Equation name is 'load7', type is output
load7 = _LC7_A21;
-- Node name is ':7'
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = !ena_scan & _LC7_A21
# _LC7_A21 & !recount;
-- Node name is ':9'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = !ena_scan & _LC2_A21
# _LC2_A21 & !recount;
-- Node name is ':11'
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = !ena_scan & _LC6_A21
# _LC6_A21 & !recount;
-- Node name is ':13'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = !ena_scan & _LC8_A21
# _LC8_A21 & !recount
# ena_scan & recount & !sign_state0;
-- Node name is ':15'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = !ena_scan & _LC4_A21
# _LC4_A21 & !recount;
-- Node name is ':17'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = _LC3_A21
# ena_scan & recount;
-- Node name is ':19'
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = !ena_scan & _LC5_A21
# _LC5_A21 & !recount;
-- Node name is ':21'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ008 = !ena_scan & _LC1_A21
# _LC1_A21 & !recount
# ena_scan & recount & sign_state0;
Project Information d:\my work\fpga\13_1908\vhdlcoder\traffic_mux.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,363K
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