📄 traffic.rpt
字号:
- 8 - A 02 AND2 0 1 1 0 |traffic_fsm:u4|:1559
- 6 - C 06 AND2 0 3 1 0 |traffic_fsm:u4|:1636
- 1 - C 06 AND2 0 3 1 0 |traffic_fsm:u4|:1637
- 1 - C 07 DFFE + 0 2 0 1 |traffic_mux:u2|:7
- 4 - C 07 DFFE + 0 2 0 2 |traffic_mux:u2|:9
- 1 - C 03 DFFE + 0 2 0 3 |traffic_mux:u2|:11
- 6 - C 01 DFFE + 0 3 0 4 |traffic_mux:u2|:13
- 1 - C 09 DFFE + 0 2 0 2 |traffic_mux:u2|:15
- 5 - C 09 DFFE + 0 2 0 3 |traffic_mux:u2|:17
- 6 - C 09 DFFE + 0 2 0 4 |traffic_mux:u2|:19
- 1 - C 02 DFFE + 0 3 0 5 |traffic_mux:u2|:21
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic.rpt
traffic
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 2/ 96( 2%) 1/ 48( 2%) 7/ 48( 14%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 23/ 96( 23%) 34/ 48( 70%) 39/ 48( 81%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic.rpt
traffic
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 54 clk
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic.rpt
traffic
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 48 reset
LCELL 7 |traffic_fsm:u4|:48
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic.rpt
traffic
** EQUATIONS **
clk : INPUT;
m : INPUT;
reset : INPUT;
st_butt : INPUT;
-- Node name is 'green0'
-- Equation name is 'green0', type is output
green0 = _LC8_C5;
-- Node name is 'green1'
-- Equation name is 'green1', type is output
green1 = _LC3_C11;
-- Node name is 'next_state'
-- Equation name is 'next_state', type is output
next_state = _LC4_C19;
-- Node name is 'recount'
-- Equation name is 'recount', type is output
recount = _LC5_C5;
-- Node name is 'red0'
-- Equation name is 'red0', type is output
red0 = _LC8_A2;
-- Node name is 'red1'
-- Equation name is 'red1', type is output
red1 = _LC7_A4;
-- Node name is 'seg70'
-- Equation name is 'seg70', type is output
seg70 = _LC3_C15;
-- Node name is 'seg71'
-- Equation name is 'seg71', type is output
seg71 = _LC6_C18;
-- Node name is 'seg72'
-- Equation name is 'seg72', type is output
seg72 = _LC7_C20;
-- Node name is 'seg73'
-- Equation name is 'seg73', type is output
seg73 = _LC5_C13;
-- Node name is 'seg74'
-- Equation name is 'seg74', type is output
seg74 = _LC7_C11;
-- Node name is 'seg75'
-- Equation name is 'seg75', type is output
seg75 = _LC7_C15;
-- Node name is 'seg76'
-- Equation name is 'seg76', type is output
seg76 = _LC1_C15;
-- Node name is 'seg77'
-- Equation name is 'seg77', type is output
seg77 = GND;
-- Node name is 'seg78'
-- Equation name is 'seg78', type is output
seg78 = _LC3_B14;
-- Node name is 'seg79'
-- Equation name is 'seg79', type is output
seg79 = _LC4_B12;
-- Node name is 'seg710'
-- Equation name is 'seg710', type is output
seg710 = _LC2_B14;
-- Node name is 'seg711'
-- Equation name is 'seg711', type is output
seg711 = _LC6_B14;
-- Node name is 'seg712'
-- Equation name is 'seg712', type is output
seg712 = _LC5_B14;
-- Node name is 'seg713'
-- Equation name is 'seg713', type is output
seg713 = _LC7_B14;
-- Node name is 'seg714'
-- Equation name is 'seg714', type is output
seg714 = _LC1_B14;
-- Node name is 'seg715'
-- Equation name is 'seg715', type is output
seg715 = GND;
-- Node name is 'sign_state0'
-- Equation name is 'sign_state0', type is output
sign_state0 = _LC3_C5;
-- Node name is 'sign_state1'
-- Equation name is 'sign_state1', type is output
sign_state1 = _LC5_C4;
-- Node name is 'yellow0'
-- Equation name is 'yellow0', type is output
yellow0 = _LC1_C6;
-- Node name is 'yellow1'
-- Equation name is 'yellow1', type is output
yellow1 = _LC6_C6;
-- Node name is '|clk_gen:u1|:7' = '|clk_gen:u1|clk_scan_ff0'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = DFFE(!_LC6_C3, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
-- Node name is '|clk_gen:u1|:6' = '|clk_gen:u1|clk_scan_ff1'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = !_LC3_C3 & _LC6_C3
# _LC3_C3 & !_LC6_C3;
-- Node name is '|clk_gen:u1|:17' = '|clk_gen:u1|clk_2Hz_ff0'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = !_LC5_C11 & _LC8_C12
# !_LC2_C3 & _LC5_C11;
-- Node name is '|clk_gen:u1|:16' = '|clk_gen:u1|clk_2Hz_ff1'
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = !_LC4_C11 & _LC5_C11 & _LC8_C12
# _LC4_C11 & !_LC5_C11 & _LC8_C12
# !_LC2_C3 & _LC4_C11;
-- Node name is '|clk_gen:u1|:15' = '|clk_gen:u1|clk_2Hz_ff2'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = _LC2_C11 & !_LC6_C11 & _LC8_C12
# !_LC2_C11 & _LC6_C11 & _LC8_C12
# !_LC2_C3 & _LC2_C11;
-- Node name is '|clk_gen:u1|:14' = '|clk_gen:u1|clk_2Hz_ff3'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = !_LC1_C11 & _LC4_C6 & _LC5_C12
# _LC1_C11 & _LC2_C3 & !_LC4_C6
# !_LC2_C3 & _LC4_C6;
-- Node name is '|clk_gen:u1|:13' = '|clk_gen:u1|clk_2Hz_ff4'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = !_LC1_C12 & _LC2_C12 & _LC8_C12
# _LC1_C12 & !_LC2_C12 & _LC8_C12
# !_LC2_C3 & _LC2_C12;
-- Node name is '|clk_gen:u1|:12' = '|clk_gen:u1|clk_2Hz_ff5'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = !_LC3_C12 & _LC4_C12 & _LC8_C12
# _LC3_C12 & !_LC4_C12 & _LC8_C12
# !_LC2_C3 & _LC4_C12;
-- Node name is '|clk_gen:u1|:11' = '|clk_gen:u1|clk_2Hz_ff6'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ008 = !_LC6_C12 & _LC7_C12 & _LC8_C12
# _LC6_C12 & !_LC7_C12 & _LC8_C12
# !_LC2_C3 & _LC7_C12;
-- Node name is '|clk_gen:u1|:9' = '|clk_gen:u1|ena_one'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = DFFE( _EQ009, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ009 = !_LC4_C6 & _LC8_C6
# _LC5_C12 & _LC8_C6
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