📄 traffic.rpt
字号:
traffic
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
42 - - - -- INPUT 0 0 0 3 m
2 - - - -- INPUT G 0 0 0 1 reset
44 - - - -- INPUT 0 0 0 1 st_butt
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic.rpt
traffic
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
35 - - - 06 OUTPUT 0 1 0 0 green0
28 - - C -- OUTPUT 0 1 0 0 green1
60 - - C -- OUTPUT 0 1 0 0 next_state
29 - - C -- OUTPUT 0 1 0 0 recount
18 - - A -- OUTPUT 0 1 0 0 red0
19 - - A -- OUTPUT 0 1 0 0 red1
49 - - - 16 OUTPUT 0 1 0 0 seg70
51 - - - 18 OUTPUT 0 1 0 0 seg71
53 - - - 20 OUTPUT 0 1 0 0 seg72
59 - - C -- OUTPUT 0 1 0 0 seg73
30 - - C -- OUTPUT 0 1 0 0 seg74
58 - - C -- OUTPUT 0 1 0 0 seg75
62 - - C -- OUTPUT 0 1 0 0 seg76
37 - - - 09 OUTPUT 0 0 0 0 seg77
66 - - B -- OUTPUT 0 1 0 0 seg78
23 - - B -- OUTPUT 0 1 0 0 seg79
22 - - B -- OUTPUT 0 1 0 0 seg710
24 - - B -- OUTPUT 0 1 0 0 seg711
65 - - B -- OUTPUT 0 1 0 0 seg712
64 - - B -- OUTPUT 0 1 0 0 seg713
67 - - B -- OUTPUT 0 1 0 0 seg714
17 - - A -- OUTPUT 0 0 0 0 seg715
61 - - C -- OUTPUT 0 1 0 0 sign_state0
7 - - - 03 OUTPUT 0 1 0 0 sign_state1
27 - - C -- OUTPUT 0 1 0 0 yellow0
5 - - - 05 OUTPUT 0 1 0 0 yellow1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my work\fpga\13_1908\vhdlcoder\traffic.rpt
traffic
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 11 AND2 0 2 0 2 |clk_gen:u1|LPM_ADD_SUB:247|addcore:adder|:67
- 1 - C 11 AND2 0 2 0 2 |clk_gen:u1|LPM_ADD_SUB:247|addcore:adder|:71
- 1 - C 12 AND2 0 2 0 2 |clk_gen:u1|LPM_ADD_SUB:247|addcore:adder|:75
- 3 - C 12 AND2 0 2 0 2 |clk_gen:u1|LPM_ADD_SUB:247|addcore:adder|:79
- 6 - C 12 AND2 0 2 0 1 |clk_gen:u1|LPM_ADD_SUB:247|addcore:adder|:83
- 3 - C 03 DFFE + 0 1 0 1 |clk_gen:u1|clk_scan_ff1 (|clk_gen:u1|:6)
- 6 - C 03 DFFE + 0 0 0 2 |clk_gen:u1|clk_scan_ff0 (|clk_gen:u1|:7)
- 2 - C 03 DFFE + 0 2 0 29 |clk_gen:u1|ena_s (|clk_gen:u1|:8)
- 8 - C 06 DFFE + 0 3 0 4 |clk_gen:u1|ena_one (|clk_gen:u1|:9)
- 7 - C 06 DFFE + 0 3 0 2 |clk_gen:u1|ena_two (|clk_gen:u1|:10)
- 7 - C 12 DFFE + 0 3 0 1 |clk_gen:u1|clk_2Hz_ff6 (|clk_gen:u1|:11)
- 4 - C 12 DFFE + 0 3 0 2 |clk_gen:u1|clk_2Hz_ff5 (|clk_gen:u1|:12)
- 2 - C 12 DFFE + 0 3 0 2 |clk_gen:u1|clk_2Hz_ff4 (|clk_gen:u1|:13)
- 4 - C 06 DFFE + 0 3 0 4 |clk_gen:u1|clk_2Hz_ff3 (|clk_gen:u1|:14)
- 2 - C 11 DFFE + 0 3 0 2 |clk_gen:u1|clk_2Hz_ff2 (|clk_gen:u1|:15)
- 4 - C 11 DFFE + 0 3 0 1 |clk_gen:u1|clk_2Hz_ff1 (|clk_gen:u1|:16)
- 5 - C 11 DFFE + 0 2 0 2 |clk_gen:u1|clk_2Hz_ff0 (|clk_gen:u1|:17)
- 5 - C 12 OR2 s 0 4 0 4 |clk_gen:u1|~170~1
- 8 - C 12 OR2 s 0 3 0 6 |clk_gen:u1|~376~1
- 5 - C 06 OR2 ! 0 3 0 8 |clk_gen:u1|:435
- 4 - C 09 OR2 0 4 0 4 |count_down:u3|LPM_ADD_SUB:695|addcore:adder|pcarry3
- 4 - C 03 OR2 0 3 0 1 |count_down:u3|LPM_ADD_SUB:695|addcore:adder|pcarry5
- 4 - C 02 OR2 0 2 0 1 |count_down:u3|LPM_ADD_SUB:695|addcore:adder|:149
- 3 - C 09 OR2 0 4 0 1 |count_down:u3|LPM_ADD_SUB:695|addcore:adder|:151
- 4 - C 01 OR2 0 2 0 1 |count_down:u3|LPM_ADD_SUB:695|addcore:adder|:152
- 5 - C 03 OR2 0 4 0 1 |count_down:u3|LPM_ADD_SUB:695|addcore:adder|:154
- 3 - C 10 OR2 0 3 0 5 |count_down:u3|LPM_ADD_SUB:736|addcore:adder|pcarry2
- 1 - C 01 OR2 0 2 0 3 |count_down:u3|LPM_ADD_SUB:736|addcore:adder|pcarry3
- 8 - C 01 OR2 0 3 0 3 |count_down:u3|LPM_ADD_SUB:736|addcore:adder|pcarry5
- 1 - B 14 DFFE + 0 3 1 0 |count_down:u3|:15
- 7 - B 14 DFFE + 0 3 1 0 |count_down:u3|:17
- 5 - B 14 DFFE + 0 2 1 0 |count_down:u3|:19
- 6 - B 14 DFFE + 0 2 1 0 |count_down:u3|:21
- 2 - B 14 DFFE + 0 3 1 0 |count_down:u3|:23
- 4 - B 12 DFFE + 0 0 1 0 |count_down:u3|:25
- 3 - B 14 DFFE + 0 2 1 0 |count_down:u3|:27
- 1 - C 15 DFFE + 0 4 1 0 |count_down:u3|:31
- 7 - C 15 DFFE + 0 4 1 0 |count_down:u3|:33
- 7 - C 11 DFFE + 0 4 1 0 |count_down:u3|:35
- 5 - C 13 DFFE + 0 4 1 0 |count_down:u3|:37
- 7 - C 20 DFFE + 0 4 1 0 |count_down:u3|:39
- 6 - C 18 DFFE + 0 4 1 0 |count_down:u3|:41
- 3 - C 15 DFFE + 0 4 1 0 |count_down:u3|:43
- 6 - C 07 DFFE + 0 3 0 3 |count_down:u3|cnt_ff7 (|count_down:u3|:46)
- 2 - C 09 DFFE + 0 2 0 4 |count_down:u3|cnt_ff6 (|count_down:u3|:47)
- 2 - C 01 DFFE + 0 3 0 3 |count_down:u3|cnt_ff5 (|count_down:u3|:48)
- 7 - C 01 DFFE + 0 2 0 35 |count_down:u3|cnt_ff4 (|count_down:u3|:49)
- 7 - C 02 DFFE + 0 2 0 32 |count_down:u3|cnt_ff3 (|count_down:u3|:50)
- 8 - C 10 DFFE + 0 3 0 15 |count_down:u3|cnt_ff2 (|count_down:u3|:51)
- 2 - C 02 DFFE + 0 2 0 8 |count_down:u3|cnt_ff1 (|count_down:u3|:52)
- 6 - C 02 DFFE + 0 3 0 8 |count_down:u3|cnt_ff0 (|count_down:u3|:53)
- 3 - C 07 OR2 0 4 0 1 |count_down:u3|:763
- 5 - C 07 OR2 0 4 0 1 |count_down:u3|:764
- 7 - C 09 OR2 0 4 0 1 |count_down:u3|:768
- 7 - C 03 OR2 0 4 0 1 |count_down:u3|:775
- 3 - C 01 OR2 0 4 0 1 |count_down:u3|:776
- 5 - C 01 OR2 0 4 0 1 |count_down:u3|:780
- 3 - C 02 OR2 0 4 0 1 |count_down:u3|:786
- 8 - C 09 OR2 0 4 0 1 |count_down:u3|:793
- 2 - C 10 OR2 0 4 0 1 |count_down:u3|:794
- 5 - C 02 OR2 0 4 0 1 |count_down:u3|:798
- 5 - C 10 AND2 s 0 4 0 7 |count_down:u3|~3878~1
- 1 - C 10 AND2 s 0 4 0 7 |count_down:u3|~3898~1
- 4 - C 24 OR2 ! 0 4 0 4 |count_down:u3|:3918
- 6 - C 10 OR2 s ! 0 4 0 8 |count_down:u3|~3958~1
- 7 - C 22 OR2 ! 0 3 0 1 |count_down:u3|:3958
- 5 - C 24 OR2 ! 0 4 0 3 |count_down:u3|:3978
- 6 - C 22 AND2 0 4 0 3 |count_down:u3|:3998
- 7 - C 10 AND2 s 0 3 0 4 |count_down:u3|~4018~1
- 5 - C 22 AND2 0 4 0 4 |count_down:u3|:4018
- 3 - C 16 OR2 s ! 0 2 0 1 |count_down:u3|~4038~1
- 7 - C 19 OR2 ! 0 3 0 5 |count_down:u3|:4038
- 8 - C 23 AND2 0 3 0 7 |count_down:u3|:4118
- 1 - C 21 AND2 0 4 0 2 |count_down:u3|:4138
- 5 - C 17 AND2 0 4 0 2 |count_down:u3|:4158
- 4 - C 17 OR2 ! 0 4 0 5 |count_down:u3|:4178
- 2 - C 07 OR2 s 0 3 0 8 |count_down:u3|~4218~1
- 3 - C 19 AND2 0 3 0 5 |count_down:u3|:4218
- 8 - C 17 OR2 ! 0 4 0 5 |count_down:u3|:4238
- 3 - C 17 AND2 s ! 0 2 0 4 |count_down:u3|~4258~1
- 1 - C 20 AND2 0 4 0 2 |count_down:u3|:4298
- 4 - C 10 AND2 s ! 0 3 0 6 |count_down:u3|~4318~1
- 7 - C 17 AND2 0 4 0 8 |count_down:u3|:4318
- 1 - C 17 AND2 0 4 0 2 |count_down:u3|:4338
- 1 - C 19 OR2 s 0 2 0 6 |count_down:u3|~4378~1
- 5 - C 19 OR2 ! 0 2 0 4 |count_down:u3|:4378
- 2 - C 17 AND2 s ! 0 3 0 3 |count_down:u3|~4398~1
- 7 - C 21 AND2 0 2 0 3 |count_down:u3|:4398
- 2 - C 20 AND2 s ! 0 2 0 3 |count_down:u3|~4418~1
- 6 - C 20 AND2 0 2 0 3 |count_down:u3|:4418
- 8 - C 07 AND2 0 3 0 5 |count_down:u3|:4458
- 8 - C 24 OR2 s ! 0 4 0 1 |count_down:u3|~4494~1
- 2 - C 24 AND2 ! 0 4 0 3 |count_down:u3|:4494
- 1 - C 18 OR2 s 0 4 0 6 |count_down:u3|~4647~1
- 5 - C 15 OR2 s ! 0 3 0 2 |count_down:u3|~4715~1
- 7 - C 16 AND2 0 4 0 6 |count_down:u3|:4715
- 2 - C 05 OR2 s 0 2 0 4 |count_down:u3|~4740~1
- 8 - C 18 OR2 s 0 2 0 1 |count_down:u3|~4740~2
- 7 - C 24 OR2 0 4 0 2 |count_down:u3|:5214
- 1 - C 22 OR2 s 0 2 0 3 |count_down:u3|~5232~1
- 3 - C 22 OR2 s 0 3 0 2 |count_down:u3|~5232~2
- 3 - C 24 OR2 0 4 0 1 |count_down:u3|:5232
- 2 - C 19 OR2 s ! 0 4 0 2 |count_down:u3|~5243~1
- 4 - C 15 OR2 0 4 0 1 |count_down:u3|:5252
- 6 - C 21 OR2 s 0 4 0 3 |count_down:u3|~5262~1
- 6 - C 15 OR2 0 4 0 1 |count_down:u3|:5262
- 8 - C 15 OR2 0 4 0 1 |count_down:u3|:5282
- 6 - C 13 OR2 0 4 0 1 |count_down:u3|:5337
- 8 - C 13 OR2 0 4 0 1 |count_down:u3|:5349
- 7 - C 13 AND2 0 3 0 1 |count_down:u3|:5363
- 5 - C 20 OR2 s 0 4 0 4 |count_down:u3|~5367~1
- 2 - C 15 OR2 0 4 0 1 |count_down:u3|:5379
- 8 - C 22 OR2 0 4 0 1 |count_down:u3|:5418
- 2 - C 22 OR2 0 4 0 1 |count_down:u3|:5438
- 3 - C 21 OR2 0 4 0 1 |count_down:u3|:5450
- 5 - C 21 OR2 0 4 0 1 |count_down:u3|:5460
- 8 - C 21 OR2 s 0 4 0 1 |count_down:u3|~5480~1
- 2 - C 21 OR2 0 4 0 1 |count_down:u3|:5480
- 1 - C 24 AND2 0 2 0 2 |count_down:u3|:5510
- 1 - C 13 OR2 0 4 0 1 |count_down:u3|:5523
- 2 - C 13 OR2 0 4 0 1 |count_down:u3|:5540
- 8 - C 20 OR2 s 0 4 0 4 |count_down:u3|~5553~1
- 3 - C 13 OR2 0 4 0 1 |count_down:u3|:5553
- 4 - C 13 OR2 0 4 0 1 |count_down:u3|:5570
- 4 - C 16 OR2 0 4 0 1 |count_down:u3|:5610
- 4 - C 21 OR2 s 0 2 0 6 |count_down:u3|~5631~1
- 5 - C 16 OR2 s 0 4 0 1 |count_down:u3|~5631~2
- 6 - C 16 OR2 0 4 0 1 |count_down:u3|:5640
- 8 - C 16 OR2 0 4 0 1 |count_down:u3|:5648
- 6 - C 19 OR2 s 0 3 0 5 |count_down:u3|~5661~1
- 6 - C 14 OR2 s 0 2 0 3 |count_down:u3|~5661~2
- 3 - C 20 OR2 s 0 4 0 1 |count_down:u3|~5661~3
- 4 - C 22 OR2 0 4 0 2 |count_down:u3|:5693
- 4 - C 18 OR2 0 4 0 1 |count_down:u3|:5712
- 6 - C 17 OR2 s 0 4 0 4 |count_down:u3|~5742~1
- 5 - C 18 OR2 s 0 4 0 1 |count_down:u3|~5742~2
- 7 - C 18 OR2 0 4 0 1 |count_down:u3|:5742
- 2 - C 18 OR2 s ! 0 2 0 2 |count_down:u3|~5763~1
- 6 - C 24 AND2 0 2 0 3 |count_down:u3|:5798
- 2 - C 16 OR2 s 0 3 0 3 |count_down:u3|~5811~1
- 1 - C 16 OR2 s 0 4 0 5 |count_down:u3|~5811~2
- 3 - C 18 OR2 s 0 2 0 1 |count_down:u3|~5811~3
- 1 - C 14 OR2 0 4 0 1 |count_down:u3|:5811
- 8 - C 19 OR2 s 0 4 0 4 |count_down:u3|~5820~1
- 2 - C 14 OR2 0 3 0 1 |count_down:u3|:5820
- 3 - C 14 OR2 s 0 3 0 1 |count_down:u3|~5841~1
- 4 - C 14 OR2 0 4 0 1 |count_down:u3|:5849
- 4 - C 20 OR2 s 0 2 0 5 |count_down:u3|~5850~1
- 4 - C 19 AND2 0 2 1 8 |count_down:u3|:5956
- 2 - A 10 OR2 0 2 0 5 |traffic_fsm:u4|LPM_ADD_SUB:109|addcore:adder|pcarry1
- 4 - A 06 OR2 0 2 0 1 |traffic_fsm:u4|LPM_ADD_SUB:109|addcore:adder|pcarry2
- 7 - A 06 OR2 0 3 0 1 |traffic_fsm:u4|LPM_ADD_SUB:109|addcore:adder|pcarry3
- 1 - A 06 OR2 0 4 0 1 |traffic_fsm:u4|LPM_ADD_SUB:109|addcore:adder|pcarry4
- 5 - C 05 DFFE + ! 0 4 1 20 |traffic_fsm:u4|:9
- 5 - C 04 DFFE + 0 4 1 2 |traffic_fsm:u4|:11
- 3 - C 05 DFFE + ! 0 3 1 4 |traffic_fsm:u4|:13
- 8 - A 10 DFFE + 0 4 0 1 |traffic_fsm:u4|st_transfer (|traffic_fsm:u4|:21)
- 2 - C 04 DFFE + 0 3 0 9 |traffic_fsm:u4|state1 (|traffic_fsm:u4|:23)
- 7 - C 04 DFFE + 0 2 0 10 |traffic_fsm:u4|state0 (|traffic_fsm:u4|:24)
- 3 - A 10 DFFE + ! 0 4 0 1 |traffic_fsm:u4|rebn_ff5 (|traffic_fsm:u4|:36)
- 8 - A 06 DFFE + ! 0 4 0 2 |traffic_fsm:u4|rebn_ff4 (|traffic_fsm:u4|:37)
- 5 - A 06 DFFE + ! 0 4 0 3 |traffic_fsm:u4|rebn_ff3 (|traffic_fsm:u4|:38)
- 6 - A 06 DFFE + ! 0 4 0 4 |traffic_fsm:u4|rebn_ff2 (|traffic_fsm:u4|:39)
- 5 - A 10 DFFE + ! 0 4 0 3 |traffic_fsm:u4|rebn_ff1 (|traffic_fsm:u4|:40)
- 6 - A 10 DFFE + ! 0 4 0 4 |traffic_fsm:u4|rebn_ff0 (|traffic_fsm:u4|:41)
- 3 - A 06 AND2 ! 2 0 0 7 |traffic_fsm:u4|:48
- 1 - A 10 OR2 s 0 3 0 1 |traffic_fsm:u4|~70~1
- 2 - A 06 AND2 0 4 0 7 |traffic_fsm:u4|:70
- 7 - A 10 AND2 s 0 2 0 1 |traffic_fsm:u4|~218~1
- 2 - C 06 AND2 1 3 0 6 |traffic_fsm:u4|:620
- 4 - A 10 OR2 ! 1 2 0 4 |traffic_fsm:u4|:799
- 3 - C 04 OR2 0 4 0 2 |traffic_fsm:u4|:801
- 1 - C 04 OR2 0 4 0 4 |traffic_fsm:u4|:1259
- 8 - C 05 AND2 0 2 1 2 |traffic_fsm:u4|:1324
- 3 - C 06 OR2 s ! 1 3 0 1 |traffic_fsm:u4|~1344~1
- 3 - C 11 OR2 ! 0 2 1 3 |traffic_fsm:u4|:1344
- 7 - C 05 AND2 s ! 0 3 0 1 |traffic_fsm:u4|~1347~1
- 4 - C 04 OR2 s 0 2 0 1 |traffic_fsm:u4|~1407~1
- 6 - C 04 OR2 s 0 4 0 1 |traffic_fsm:u4|~1407~2
- 8 - C 04 OR2 s 0 4 0 1 |traffic_fsm:u4|~1407~3
- 1 - C 05 OR2 s ! 0 4 0 1 |traffic_fsm:u4|~1422~1
- 4 - C 05 OR2 s ! 0 3 0 1 |traffic_fsm:u4|~1422~2
- 6 - C 05 OR2 s ! 0 4 0 1 |traffic_fsm:u4|~1422~3
- 7 - A 04 AND2 0 1 1 0 |traffic_fsm:u4|:1546
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