📄 alarm_set.rpt
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# sec_tmp5 & !sec_tune
# !_LC2_B21 & sec_tmp5;
-- Node name is 'sec0'
-- Equation name is 'sec0', type is output
sec0 = sec_tmp0;
-- Node name is 'sec1'
-- Equation name is 'sec1', type is output
sec1 = sec_tmp1;
-- Node name is 'sec2'
-- Equation name is 'sec2', type is output
sec2 = sec_tmp2;
-- Node name is 'sec3'
-- Equation name is 'sec3', type is output
sec3 = sec_tmp3;
-- Node name is 'sec4'
-- Equation name is 'sec4', type is output
sec4 = sec_tmp4;
-- Node name is 'sec5'
-- Equation name is 'sec5', type is output
sec5 = sec_tmp5;
-- Node name is '|LPM_ADD_SUB:203|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A16', type is buried
!_LC1_A16 = _LC1_A16~NOT;
_LC1_A16~NOT = LCELL( _EQ018);
_EQ018 = !sec_tmp1
# !sec_tmp0;
-- Node name is '|LPM_ADD_SUB:203|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = LCELL( _EQ019);
_EQ019 = sec_tmp0 & sec_tmp1 & sec_tmp2 & sec_tmp3;
-- Node name is '|LPM_ADD_SUB:370|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B15', type is buried
!_LC2_B15 = _LC2_B15~NOT;
_LC2_B15~NOT = LCELL( _EQ020);
_EQ020 = !min_tmp1
# !min_tmp0;
-- Node name is '|LPM_ADD_SUB:370|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B15', type is buried
_LC7_B15 = LCELL( _EQ021);
_EQ021 = min_tmp0 & min_tmp1 & min_tmp2 & min_tmp3;
-- Node name is '|LPM_ADD_SUB:528|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C18', type is buried
!_LC2_C18 = _LC2_C18~NOT;
_LC2_C18~NOT = LCELL( _EQ022);
_EQ022 = !hour_tmp2
# !hour_tmp1
# !hour_tmp0;
-- Node name is ':138'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ023);
_EQ023 = alarm & !ok;
-- Node name is '~159~1'
-- Equation name is '~159~1', location is LC2_A16, type is buried.
-- synthesized logic cell
_LC2_A16 = LCELL( _EQ024);
_EQ024 = !sec_tmp4
# !sec_tmp5
# !sec_tmp3;
-- Node name is '~280~1'
-- Equation name is '~280~1', location is LC8_A16, type is buried.
-- synthesized logic cell
_LC8_A16 = LCELL( _EQ025);
_EQ025 = sec_tmp2 & sec_tune
# !_LC1_A16 & sec_tune
# _LC2_A16 & sec_tune;
-- Node name is ':280'
-- Equation name is '_LC7_A17', type is buried
_LC7_A17 = LCELL( _EQ026);
_EQ026 = _LC8_A16 & !sec_tmp4 & sec_tmp5
# !_LC3_A16 & _LC8_A16 & sec_tmp5
# _LC3_A16 & _LC8_A16 & sec_tmp4 & !sec_tmp5;
-- Node name is ':286'
-- Equation name is '_LC5_A17', type is buried
_LC5_A17 = LCELL( _EQ027);
_EQ027 = !_LC3_A16 & _LC8_A16 & sec_tmp4
# _LC3_A16 & _LC8_A16 & !sec_tmp4;
-- Node name is ':292'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ028);
_EQ028 = _LC8_A16 & !sec_tmp2 & sec_tmp3
# !_LC1_A16 & _LC8_A16 & sec_tmp3
# _LC1_A16 & _LC8_A16 & sec_tmp2 & !sec_tmp3;
-- Node name is ':298'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = LCELL( _EQ029);
_EQ029 = !_LC1_A16 & _LC8_A16 & sec_tmp2
# _LC1_A16 & _LC8_A16 & !sec_tmp2;
-- Node name is ':304'
-- Equation name is '_LC2_A17', type is buried
_LC2_A17 = LCELL( _EQ030);
_EQ030 = _LC8_A16 & !sec_tmp0 & sec_tmp1
# _LC8_A16 & sec_tmp0 & !sec_tmp1;
-- Node name is '~326~1'
-- Equation name is '~326~1', location is LC5_B15, type is buried.
-- synthesized logic cell
_LC5_B15 = LCELL( _EQ031);
_EQ031 = !min_tmp4
# !min_tmp5
# !min_tmp3;
-- Node name is '~447~1'
-- Equation name is '~447~1', location is LC4_B15, type is buried.
-- synthesized logic cell
_LC4_B15 = LCELL( _EQ032);
_EQ032 = min_tmp2 & min_tune
# !_LC2_B15 & min_tune
# _LC5_B15 & min_tune;
-- Node name is ':447'
-- Equation name is '_LC8_B21', type is buried
_LC8_B21 = LCELL( _EQ033);
_EQ033 = _LC4_B15 & !min_tmp4 & min_tmp5
# _LC4_B15 & !_LC7_B15 & min_tmp5
# _LC4_B15 & _LC7_B15 & min_tmp4 & !min_tmp5;
-- Node name is ':453'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ034);
_EQ034 = _LC4_B15 & !_LC7_B15 & min_tmp4
# _LC4_B15 & _LC7_B15 & !min_tmp4;
-- Node name is ':459'
-- Equation name is '_LC8_B15', type is buried
_LC8_B15 = LCELL( _EQ035);
_EQ035 = _LC4_B15 & !min_tmp2 & min_tmp3
# !_LC2_B15 & _LC4_B15 & min_tmp3
# _LC2_B15 & _LC4_B15 & min_tmp2 & !min_tmp3;
-- Node name is ':465'
-- Equation name is '_LC6_B15', type is buried
_LC6_B15 = LCELL( _EQ036);
_EQ036 = !_LC2_B15 & _LC4_B15 & min_tmp2
# _LC2_B15 & _LC4_B15 & !min_tmp2;
-- Node name is ':471'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ037);
_EQ037 = _LC4_B15 & !min_tmp0 & min_tmp1
# _LC4_B15 & min_tmp0 & !min_tmp1;
-- Node name is ':594'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ038);
_EQ038 = hour_tmp3 & !hour_tmp4 & hour_tune & _LC2_C18
# hour_tmp4 & !_LC2_C18
# hour_tmp4 & !hour_tune;
-- Node name is '~595~1'
-- Equation name is '~595~1', location is LC4_C18, type is buried.
-- synthesized logic cell
_LC4_C18 = LCELL( _EQ039);
_EQ039 = hour_tune & !_LC2_C18
# !hour_tmp4 & hour_tune
# hour_tmp3 & hour_tune;
-- Node name is ':601'
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = LCELL( _EQ040);
_EQ040 = hour_tmp3 & hour_tune & !_LC2_C18
# !hour_tmp3 & !hour_tmp4 & hour_tune & _LC2_C18;
-- Node name is ':607'
-- Equation name is '_LC7_C18', type is buried
_LC7_C18 = LCELL( _EQ041);
_EQ041 = !hour_tmp1 & hour_tmp2 & _LC4_C18
# !hour_tmp0 & hour_tmp2 & _LC4_C18
# hour_tmp0 & hour_tmp1 & !hour_tmp2 & _LC4_C18;
-- Node name is ':613'
-- Equation name is '_LC6_C18', type is buried
_LC6_C18 = LCELL( _EQ042);
_EQ042 = !hour_tmp0 & hour_tmp1 & _LC4_C18
# hour_tmp0 & !hour_tmp1 & _LC4_C18;
Project Information d:\my work\fpga\13_1908\vhdlcoder\alarm_set.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,652K
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