bin_nul.vhd

交通灯程序《数字电路EDA入门－VHDL程序实例》---交通灯程序例子,,C-C++

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is 
  port(x,y,z:in std_logic;s,c:out std_logic);
end full_adder;
architecture df of full_adder is
begin
s<=(x xor y)xor z;
c<=(x and y)or(x and z)or(y and z);
end df;
--????????N???????
library ieee;
use ieee.std_logic_1164.all;
entity generic_fa is
    generic(n:natural);
    port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end generic_fa;

architecture conc of generic_fa is
  component full_adder
    port(x,y,z:in std_logic;s,c:out std_logic);
  end component;
  signal carry:std_logic_vector(n downto 0);
begin
  carry(0)<='0';
  cout<=carry(n);
  
  g1:for k in 0 to n-1 generate
   fa:full_adder port map (x=>a(k),y=>b(k),z=>carry(k),
                        s=>sum(k),c=>carry(k+1));
                    end generate;
end conc;    
--????????????
library ieee;
use ieee.std_logic_1164.all;
entity binary_multiplier is
    generic(n,m:positive);
    port(mplr:in std_logic_vector(n-1 downto 0);
         mpcd:in std_logic_vector(m-1 downto 0);
         result:out std_logic_vector(n+m-1 downto 0));
end binary_multiplier;

architecture compact of binary_multiplier is
  signal acarry:std_logic_vector(n-1 downto 0);
  type sum_type is array(n-1 downto 0) of
    std_logic_vector(m-1 downto 0);
  signal asum:sum_type;
  signal opd1,opd2:sum_type;
  signal res:std_logic_vector(n+m-1 downto 0);
  
  function resize(a:in std_logic;size:in natural)
    return std_logic_vector is
    variable res:std_logic_vector(size-1 downto 0);
begin 
    res:=(others=>a);
    return(res);
end;

component generic_fa
    generic(n:natural);
    port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end component;
begin
    g2:for k in 1 to n-1 generate
    g3:if k=1 generate
      asum(0)<=resize(mplr(0),m)and mpcd;
      result(0)<=asum(0)(0);
      acarry(0)<='0';
  end generate;
  
  opd2(k)<=acarry(k-1)& asum(k-1)(m-1 downto 1);
  opd1(k)<=resize(mplr(k),m)and mpcd;
  
  gfa:generic_fa
    generic map(n=>m)
    port map(a=>opd1(k),b=>opd2(k),sum=>asum(k),
            cout=>acarry(k));
    
    result(k)<=asum(k)(0);
end generate;
result(n+m-1 downto m-1)<=acarry(n-1)& asum(n-1)(m-1 downto 1);
end compact;