2dimensional-vector.vhd

交通灯程序《数字电路EDA入门－VHDL程序实例》---交通灯程序例子,,C-C++

-- *************************************************
-- Behavioral description of a single-port SRAM with:
-- Active High write enable (WE)
-- Rising clock edge (Clock)
-- *************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity reg_sram is

generic (width : integer:=8;
depth : integer:=8;
addr : integer:=3);
port (Data : in std_logic_vector (width-1 downto 0);
Q : out std_logic_vector (width-1 downto 0);
Clock : in std_logic;
WE : in std_logic;
Address : in std_logic_vector (addr-1 downto 0));
end reg_sram;

architecture behav of reg_sram is
type MEM is array (0 to depth-1) of std_logic_vector(width-1
downto 0);--definite the array
signal ramTmp : MEM;
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if (WE = '1') then
ramTmp (conv_integer (Address)) <= Data;
end if;
end if;
end process;
Q <= ramTmp(conv_integer(Address));
end behav;