coverlater.txt

本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码

---------d触发器-------
library ieee;
use ieee.std_logic_1164.all;

entity dff is
    port(    d:  in std_logic;
           clk:  in std_logic;
             q:  out std_logic);
end dff;

architecture rtl of dff is
  begin 
        process(clk)
        begin
        if (clk'event and clk='1')then 
             q<=d;            
         end if;
       end process;
end rtl;



----------模2加法器1----------
library ieee;
use ieee.std_logic_1164.all;

entity adder1 is
  port (a:  in std_logic;
        b:  in std_logic;
        c:  in std_logic;
      clk:  in std_logic;
        s:  out std_logic);
end adder1;
ARCHITECTURE structure of adder1 is
begin 
      process(clk)
      begin 
      if (clk'event and clk='0')then 
      s <=a xor b xor c;
      end if;
      end process;
end structure;



----------模2加法器2-------------
library ieee;
use ieee.std_logic_1164.all;

entity adder2 is
  port (a,b,c,d,clk: in std_logic;
              s: out std_logic);
end adder2;
ARCHITECTURE structure of adder2 is
  begin
      process(clk)
      begin
      if (clk'event and clk='0')then 
      s<=a xor b xor c xor d;
      end if;
      end process;  
end structure;



---------（2，1，3）卷积码编码---------
library ieee;
use ieee.std_logic_1164.all;

entity cover1 is
    port( data_in:  in std_logic; 
              clk:  in std_logic;         
         data_out1: out std_logic;
         data_out2: out std_logic);
end cover1;

ARCHITECTURE structure of cover1 is
   component dff is 
     port(d:  in  std_logic;
        clk:  in  std_logic;
          q:  out std_logic);
   end component;
   component adder1 is
     port (a,b,c,clk: in std_logic;
            s: out std_logic);
   end component;
  component adder2 is
     port (a,b,c,d,clk: in std_logic;
                 s: out std_logic);
  end component;
signal q:std_logic_vector(3 downto 0):="0000";
   begin  
     G1:dff port map (data_in,clk,q(1));
     G2:dff port map (q(1),clk,q(2));     
     G3:dff port map (q(2),clk,q(3));    
     G4:adder1 port map(data_in,q(2),q(3),clk,data_out1);
     G5:adder2 port map(data_in,q(1),q(2),q(3),clk,data_out2);
 
  end structure;