rcvr.tan.rpt

基于vhdl 的串行接口 具有完整的程序

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5ES    ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; wrn             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                       ; To                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 83.26 MHz ( period = 12.010 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[2]       ; clk        ; clk      ; None                        ; None                      ; 5.441 ns                ;
; N/A                                     ; 89.72 MHz ( period = 11.146 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[0]       ; clk        ; clk      ; None                        ; None                      ; 5.009 ns                ;
; N/A                                     ; 89.72 MHz ( period = 11.146 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[1]       ; clk        ; clk      ; None                        ; None                      ; 5.009 ns                ;
; N/A                                     ; 89.72 MHz ( period = 11.146 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[3]       ; clk        ; clk      ; None                        ; None                      ; 5.009 ns                ;
; N/A                                     ; 89.72 MHz ( period = 11.146 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[4]       ; clk        ; clk      ; None                        ; None                      ; 5.009 ns                ;
; N/A                                     ; 89.72 MHz ( period = 11.146 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[5]       ; clk        ; clk      ; None                        ; None                      ; 5.009 ns                ;
; N/A                                     ; 89.72 MHz ( period = 11.146 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[6]       ; clk        ; clk      ; None                        ; None                      ; 5.009 ns                ;
; N/A                                     ; 89.72 MHz ( period = 11.146 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] ; rcvr:inst|rbr[7]       ; clk        ; clk      ; None                        ; None                      ; 5.009 ns                ;
; N/A                                     ; 98.35 MHz ( period = 10.168 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[1] ; rcvr:inst|rbr[2]       ; clk        ; clk      ; None                        ; None                      ; 4.520 ns                ;
; N/A                                     ; 102.06 MHz ( period = 9.798 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[2] ; rcvr:inst|rbr[2]       ; clk        ; clk      ; None                        ; None                      ; 4.335 ns                ;
; N/A                                     ; 103.43 MHz ( period = 9.668 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[2] ; rcvr:inst|rsr[2]       ; clk        ; clk      ; None                        ; None                      ; 4.270 ns                ;
; N/A                                     ; 103.43 MHz ( period = 9.668 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[2] ; rcvr:inst|rsr[3]       ; clk        ; clk      ; None                        ; None                      ; 4.270 ns                ;
; N/A                                     ; 103.43 MHz ( period = 9.668 ns )                    ; rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[2] ; rcvr:inst|rsr[7]       ; clk        ; clk      ; None                        ; None                      ; 4.270 ns                ;
; N/A                                     ; 106.72 MHz ( period = 9.370 ns )                    ; rcvr:inst|clk1x_enable                                                     ; rcvr:inst|clk1x        ; clk        ; clk      ; None                        ; None                      ; 6.166 ns                ;