rcvr.vhd

基于vhdl 的串行接口 具有完整的程序

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity rcvr is
port (
	clk,rxd : in std_logic ;
	dout : out std_logic_vector (7 downto 0)
	) ;
end rcvr ;

architecture v1 of rcvr is

signal counter1 : integer RANGE 0 TO 17;
signal counter2 : integer RANGE 0 TO 287;
signal rxd1 : std_logic ;
signal rxd2 : std_logic ;
signal rsr : unsigned (7 downto 0) ;
signal rbr : unsigned (7 downto 0) ;
signal no_bits_rcvd : unsigned (3 downto 0) ;
signal clk1x,clk16x,clk1x_enable : std_logic ;

begin

process(clk,counter1,clk16x)
begin
	if rising_edge(clk) then
		if counter1=17 then
			counter1<=0;
			clk16x<=not clk16x;
		else
		 counter1<=counter1+1;
		end if;
	end if;
end process;	
--***************************************************************
-- 16 divided clock
process (clk,clk1x_enable)
begin
	if clk'event and clk = '1' then
		if clk1x_enable = '1' then
		IF counter2=287 then
		counter2<=0;
		clk1x<=not clk1x;
		else counter2<=counter2+1;
		end if;
		end if ;
	end if ;
end process ;
	
process (clk16x)
begin
	if  clk16x'event and clk16x = '1' then
		rxd2 <= rxd1 ;
		rxd1 <= rxd ;
	end if ;
end process ;

--***************************************************************
--clk1x_enable
process (clk16x,rxd1,rxd2,no_bits_rcvd)
begin
	if  std_logic_vector(no_bits_rcvd) = "1100" then
		clk1x_enable <= '0' ;
	elsif clk16x'event and clk16x = '1' then
		if rxd1 = '0' and rxd2 = '1' then
			clk1x_enable <= '1' ;
		end if ;
	end if ;
end process  ;
--**********************************************************************

process (clk1x)
begin
	if clk1x'event and clk1x = '0' then
		if std_logic_vector(no_bits_rcvd) >= "0000" and std_logic_vector(no_bits_rcvd) <= "1000" then
			rsr(7 downto 1) <= rsr(6 downto 0) ;
			rsr(0) <= rxd2 ;
		elsif std_logic_vector(no_bits_rcvd) = "1001" then
			rbr <= rsr ;
		end if ;
	end if ;
end process ;

--**************************************************************************************
--count the number of bits received.
process (clk1x,clk1x_enable,no_bits_rcvd)
begin
	if clk1x_enable = '0'  then
		no_bits_rcvd <= "0000" ;
	elsif clk1x'event and clk1x = '1' then
		if clk1x_enable = '1' then
			no_bits_rcvd <= no_bits_rcvd + "0001" ;
		end if ;
	end if ;
end process ;

dout <= std_logic_vector(rbr) ;
end ;