rcvr.map.eqn

基于vhdl 的串行接口 具有完整的程序

--C1_sdo is txt:inst1|sdo
--operation mode is normal

C1_sdo_lut_out = C1L25 & C1_tsr[0] & !C1L35 # !C1L25 & C1_sdo # !C1L35;
C1_sdo = DFFEAS(C1_sdo_lut_out, C1_clk1x, VCC, , , , , , );


--B1_rbr[7] is rcvr:inst|rbr[7]
--operation mode is normal

B1_rbr[7]_lut_out = B1_rsr[7];
B1_rbr[7] = DFFEAS(B1_rbr[7]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--B1_rbr[6] is rcvr:inst|rbr[6]
--operation mode is normal

B1_rbr[6]_lut_out = B1_rsr[6];
B1_rbr[6] = DFFEAS(B1_rbr[6]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--B1_rbr[5] is rcvr:inst|rbr[5]
--operation mode is normal

B1_rbr[5]_lut_out = B1_rsr[5];
B1_rbr[5] = DFFEAS(B1_rbr[5]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--B1_rbr[4] is rcvr:inst|rbr[4]
--operation mode is normal

B1_rbr[4]_lut_out = B1_rsr[4];
B1_rbr[4] = DFFEAS(B1_rbr[4]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--B1_rbr[3] is rcvr:inst|rbr[3]
--operation mode is normal

B1_rbr[3]_lut_out = B1_rsr[3];
B1_rbr[3] = DFFEAS(B1_rbr[3]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--B1_rbr[2] is rcvr:inst|rbr[2]
--operation mode is normal

B1_rbr[2]_lut_out = B1_rsr[2];
B1_rbr[2] = DFFEAS(B1_rbr[2]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--B1_rbr[1] is rcvr:inst|rbr[1]
--operation mode is normal

B1_rbr[1]_lut_out = B1_rsr[1];
B1_rbr[1] = DFFEAS(B1_rbr[1]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--B1_rbr[0] is rcvr:inst|rbr[0]
--operation mode is normal

B1_rbr[0]_lut_out = B1_rsr[0];
B1_rbr[0] = DFFEAS(B1_rbr[0]_lut_out, !B1_clk1x, VCC, , B1L85, , , , );


--C1_tsr[0] is txt:inst1|tsr[0]
--operation mode is normal

C1_tsr[0]_lut_out = C1L74 & C1_tsr[1] # !C1L74 & C1_tbr[0];
C1_tsr[0] = DFFEAS(C1_tsr[0]_lut_out, C1_clk1x, VCC, , C1L56, , , , );


--E2_safe_q[2] is txt:inst1|lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[2]
--operation mode is arithmetic

E2_safe_q[2]_carry_eqn = E2L4;
E2_safe_q[2]_lut_out = E2_safe_q[2] $ (!E2_safe_q[2]_carry_eqn);
E2_safe_q[2] = DFFEAS(E2_safe_q[2]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );

--E2L6 is txt:inst1|lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

E2L6 = CARRY(E2_safe_q[2] & !E2L4);


--E2_safe_q[3] is txt:inst1|lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[3]
--operation mode is normal

E2_safe_q[3]_carry_eqn = E2L6;
E2_safe_q[3]_lut_out = E2_safe_q[3] $ (E2_safe_q[3]_carry_eqn);
E2_safe_q[3] = DFFEAS(E2_safe_q[3]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );


--E2_safe_q[0] is txt:inst1|lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[0]
--operation mode is arithmetic

E2_safe_q[0]_lut_out = !E2_safe_q[0];
E2_safe_q[0] = DFFEAS(E2_safe_q[0]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );

--E2L2 is txt:inst1|lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

E2L2 = CARRY(E2_safe_q[0]);


--E2_safe_q[1] is txt:inst1|lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[1]
--operation mode is arithmetic

E2_safe_q[1]_carry_eqn = E2L2;
E2_safe_q[1]_lut_out = E2_safe_q[1] $ (E2_safe_q[1]_carry_eqn);
E2_safe_q[1] = DFFEAS(E2_safe_q[1]_lut_out, C1_clk1x, C1_clk1x_enable, , , , , , );

--E2L4 is txt:inst1|lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

E2L4 = CARRY(!E2L2 # !E2_safe_q[1]);


--C1L25 is txt:inst1|sdo~451
--operation mode is normal

C1L25 = E2_safe_q[2] & !E2_safe_q[3] # !E2_safe_q[2] & E2_safe_q[3] & !E2_safe_q[1] # !E2_safe_q[0] # !E2_safe_q[3] & E2_safe_q[1];


--C1L35 is txt:inst1|sdo~452
--operation mode is normal

C1L35 = E2_safe_q[2] & E2_safe_q[3] # !E2_safe_q[2] & !E2_safe_q[3] & E2_safe_q[0] $ E2_safe_q[1];


--C1_clk1x is txt:inst1|clk1x
--operation mode is normal

C1_clk1x_lut_out = !C1_clk1x;
C1_clk1x = DFFEAS(C1_clk1x_lut_out, clk, VCC, , C1L82, , , , );


--B1_rsr[7] is rcvr:inst|rsr[7]
--operation mode is normal

B1_rsr[7]_lut_out = B1_rsr[6];
B1_rsr[7] = DFFEAS(B1_rsr[7]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--B1_clk1x is rcvr:inst|clk1x
--operation mode is normal

B1_clk1x_lut_out = !B1_clk1x;
B1_clk1x = DFFEAS(B1_clk1x_lut_out, clk, VCC, , B1L92, , , , );


--E1_safe_q[1] is rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[1]
--operation mode is arithmetic

E1_safe_q[1]_carry_eqn = E1L2;
E1_safe_q[1]_lut_out = E1_safe_q[1] $ (E1_safe_q[1]_carry_eqn);
E1_safe_q[1] = DFFEAS(E1_safe_q[1]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );

--E1L4 is rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

E1L4 = CARRY(!E1L2 # !E1_safe_q[1]);


--E1_safe_q[2] is rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[2]
--operation mode is arithmetic

E1_safe_q[2]_carry_eqn = E1L4;
E1_safe_q[2]_lut_out = E1_safe_q[2] $ (!E1_safe_q[2]_carry_eqn);
E1_safe_q[2] = DFFEAS(E1_safe_q[2]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );

--E1L6 is rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

E1L6 = CARRY(E1_safe_q[2] & !E1L4);


--E1_safe_q[0] is rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[0]
--operation mode is arithmetic

E1_safe_q[0]_lut_out = !E1_safe_q[0];
E1_safe_q[0] = DFFEAS(E1_safe_q[0]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );

--E1L2 is rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

E1L2 = CARRY(E1_safe_q[0]);


--E1_safe_q[3] is rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3]
--operation mode is normal

E1_safe_q[3]_carry_eqn = E1L6;
E1_safe_q[3]_lut_out = E1_safe_q[3] $ (E1_safe_q[3]_carry_eqn);
E1_safe_q[3] = DFFEAS(E1_safe_q[3]_lut_out, B1_clk1x, B1_clk1x_enable, , , , , , );


--B1L85 is rcvr:inst|rbr[7]~47
--operation mode is normal

B1L85 = !E1_safe_q[1] & !E1_safe_q[2] & E1_safe_q[0] & E1_safe_q[3];


--B1_rsr[6] is rcvr:inst|rsr[6]
--operation mode is normal

B1_rsr[6]_lut_out = B1_rsr[5];
B1_rsr[6] = DFFEAS(B1_rsr[6]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--B1_rsr[5] is rcvr:inst|rsr[5]
--operation mode is normal

B1_rsr[5]_lut_out = B1_rsr[4];
B1_rsr[5] = DFFEAS(B1_rsr[5]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--B1_rsr[4] is rcvr:inst|rsr[4]
--operation mode is normal

B1_rsr[4]_lut_out = B1_rsr[3];
B1_rsr[4] = DFFEAS(B1_rsr[4]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--B1_rsr[3] is rcvr:inst|rsr[3]
--operation mode is normal

B1_rsr[3]_lut_out = B1_rsr[2];
B1_rsr[3] = DFFEAS(B1_rsr[3]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--B1_rsr[2] is rcvr:inst|rsr[2]
--operation mode is normal

B1_rsr[2]_lut_out = B1_rsr[1];
B1_rsr[2] = DFFEAS(B1_rsr[2]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--B1_rsr[1] is rcvr:inst|rsr[1]
--operation mode is normal

B1_rsr[1]_lut_out = B1_rsr[0];
B1_rsr[1] = DFFEAS(B1_rsr[1]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--B1_rsr[0] is rcvr:inst|rsr[0]
--operation mode is normal

B1_rsr[0]_lut_out = B1_rxd2;
B1_rsr[0] = DFFEAS(B1_rsr[0]_lut_out, !B1_clk1x, VCC, , B1L74, , , , );


--C1_tsr[1] is txt:inst1|tsr[1]
--operation mode is normal

C1_tsr[1]_lut_out = C1L74 & C1_tsr[2] # !C1L74 & C1_tbr[1];
C1_tsr[1] = DFFEAS(C1_tsr[1]_lut_out, C1_clk1x, VCC, , C1L56, , , , );


--C1_tbr[0] is txt:inst1|tbr[0]
--operation mode is normal

C1_tbr[0]_lut_out = din[0];
C1_tbr[0] = DFFEAS(C1_tbr[0]_lut_out, !wrn, VCC, , , , , , );


--C1L74 is txt:inst1|reduce_nor~4
--operation mode is normal

C1L74 = E2_safe_q[1] # E2_safe_q[2] # E2_safe_q[3] # !E2_safe_q[0];


--C1L56 is txt:inst1|tsr[0]~642
--operation mode is normal

C1L56 = E2_safe_q[0] & !E2_safe_q[1] & !E2_safe_q[2] # !E2_safe_q[3] # !E2_safe_q[0] & E2_safe_q[2] $ E2_safe_q[3];


--C1_clk1x_enable is txt:inst1|clk1x_enable
--operation mode is normal

C1_clk1x_enable_lut_out = C1_clk1x_enable & C1L72 # C1_wrn2 & !C1_wrn1 # !C1_clk1x_enable & C1_wrn2 & !C1_wrn1;
C1_clk1x_enable = DFFEAS(C1_clk1x_enable_lut_out, C1_clk16x, VCC, , , , , , );


--C1_counter2[0] is txt:inst1|counter2[0]
--operation mode is normal

C1_counter2[0]_lut_out = C1L1;
C1_counter2[0] = DFFEAS(C1_counter2[0]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[7] is txt:inst1|counter2[7]
--operation mode is normal

C1_counter2[7]_lut_out = C1L51;
C1_counter2[7] = DFFEAS(C1_counter2[7]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[6] is txt:inst1|counter2[6]
--operation mode is normal

C1_counter2[6]_lut_out = C1L31;
C1_counter2[6] = DFFEAS(C1_counter2[6]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[5] is txt:inst1|counter2[5]
--operation mode is normal

C1_counter2[5]_lut_out = C1L11 & C1L84 # C1L94 # !C1_counter2[0];
C1_counter2[5] = DFFEAS(C1_counter2[5]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[8] is txt:inst1|counter2[8]
--operation mode is normal

C1_counter2[8]_lut_out = C1L71 & C1L84 # C1L94 # !C1_counter2[0];
C1_counter2[8] = DFFEAS(C1_counter2[8]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1L84 is txt:inst1|reduce_nor~95
--operation mode is normal

C1L84 = C1_counter2[7] # C1_counter2[6] # C1_counter2[5] # !C1_counter2[8];


--C1_counter2[4] is txt:inst1|counter2[4]
--operation mode is normal

C1_counter2[4]_lut_out = C1L9;
C1_counter2[4] = DFFEAS(C1_counter2[4]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[3] is txt:inst1|counter2[3]
--operation mode is normal

C1_counter2[3]_lut_out = C1L7;
C1_counter2[3] = DFFEAS(C1_counter2[3]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[2] is txt:inst1|counter2[2]
--operation mode is normal

C1_counter2[2]_lut_out = C1L5;
C1_counter2[2] = DFFEAS(C1_counter2[2]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1_counter2[1] is txt:inst1|counter2[1]
--operation mode is normal

C1_counter2[1]_lut_out = C1L3;
C1_counter2[1] = DFFEAS(C1_counter2[1]_lut_out, clk, VCC, , C1_clk1x_enable, , , , );


--C1L94 is txt:inst1|reduce_nor~96
--operation mode is normal

C1L94 = !C1_counter2[1] # !C1_counter2[2] # !C1_counter2[3] # !C1_counter2[4];


--C1L82 is txt:inst1|clk1x~0
--operation mode is normal

C1L82 = C1_clk1x_enable & C1_counter2[0] & !C1L84 & !C1L94;


--B1L74 is rcvr:inst|LessThan~68
--operation mode is normal

B1L74 = !E1_safe_q[1] & !E1_safe_q[2] & !E1_safe_q[0] # !E1_safe_q[3];


--B1_clk1x_enable is rcvr:inst|clk1x_enable
--operation mode is normal

B1_clk1x_enable_lut_out = VCC;
B1_clk1x_enable = DFFEAS(B1_clk1x_enable_lut_out, B1_clk16x, !B1L26, , B1L84, , , , );


--B1_counter2[0] is rcvr:inst|counter2[0]
--operation mode is normal

B1_counter2[0]_lut_out = B1L1;
B1_counter2[0] = DFFEAS(B1_counter2[0]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[7] is rcvr:inst|counter2[7]
--operation mode is normal

B1_counter2[7]_lut_out = B1L51;
B1_counter2[7] = DFFEAS(B1_counter2[7]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[6] is rcvr:inst|counter2[6]
--operation mode is normal

B1_counter2[6]_lut_out = B1L31;
B1_counter2[6] = DFFEAS(B1_counter2[6]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[5] is rcvr:inst|counter2[5]
--operation mode is normal

B1_counter2[5]_lut_out = B1L11 & B1L06 # B1L16 # !B1_counter2[0];
B1_counter2[5] = DFFEAS(B1_counter2[5]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[8] is rcvr:inst|counter2[8]
--operation mode is normal

B1_counter2[8]_lut_out = B1L71 & B1L06 # B1L16 # !B1_counter2[0];
B1_counter2[8] = DFFEAS(B1_counter2[8]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1L06 is rcvr:inst|reduce_nor~104
--operation mode is normal

B1L06 = B1_counter2[7] # B1_counter2[6] # B1_counter2[5] # !B1_counter2[8];


--B1_counter2[4] is rcvr:inst|counter2[4]
--operation mode is normal

B1_counter2[4]_lut_out = B1L9;
B1_counter2[4] = DFFEAS(B1_counter2[4]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[3] is rcvr:inst|counter2[3]
--operation mode is normal

B1_counter2[3]_lut_out = B1L7;
B1_counter2[3] = DFFEAS(B1_counter2[3]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[2] is rcvr:inst|counter2[2]
--operation mode is normal

B1_counter2[2]_lut_out = B1L5;
B1_counter2[2] = DFFEAS(B1_counter2[2]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1_counter2[1] is rcvr:inst|counter2[1]
--operation mode is normal

B1_counter2[1]_lut_out = B1L3;
B1_counter2[1] = DFFEAS(B1_counter2[1]_lut_out, clk, VCC, , B1_clk1x_enable, , , , );


--B1L16 is rcvr:inst|reduce_nor~105
--operation mode is normal

B1L16 = !B1_counter2[1] # !B1_counter2[2] # !B1_counter2[3] # !B1_counter2[4];


--B1L92 is rcvr:inst|clk1x~0
--operation mode is normal

B1L92 = B1_clk1x_enable & B1_counter2[0] & !B1L06 & !B1L16;


--B1_rxd2 is rcvr:inst|rxd2
--operation mode is normal

B1_rxd2_lut_out = B1_rxd1;
B1_rxd2 = DFFEAS(B1_rxd2_lut_out, B1_clk16x, VCC, , , , , , );


--C1_tsr[2] is txt:inst1|tsr[2]
--operation mode is normal

C1_tsr[2]_lut_out = C1L74 & C1_tsr[3] # !C1L74 & C1_tbr[2];
C1_tsr[2] = DFFEAS(C1_tsr[2]_lut_out, C1_clk1x, VCC, , C1L56, , , , );


--C1_tbr[1] is txt:inst1|tbr[1]
--operation mode is normal

C1_tbr[1]_lut_out = din[1];
C1_tbr[1] = DFFEAS(C1_tbr[1]_lut_out, !wrn, VCC, , , , , , );


--C1L72 is txt:inst1|clk1x_enable~39
--operation mode is normal

C1L72 = E2_safe_q[1] # !E2_safe_q[3] # !E2_safe_q[2] # !E2_safe_q[0];


--C1_wrn2 is txt:inst1|wrn2
--operation mode is normal

C1_wrn2_lut_out = C1_wrn1;
C1_wrn2 = DFFEAS(C1_wrn2_lut_out, C1_clk16x, VCC, , , , , , );


--C1_wrn1 is txt:inst1|wrn1
--operation mode is normal

C1_wrn1_lut_out = wrn;
C1_wrn1 = DFFEAS(C1_wrn1_lut_out, C1_clk16x, VCC, , , , , , );


--C1_clk16x is txt:inst1|clk16x
--operation mode is normal

C1_clk16x_lut_out = !C1_clk16x;
C1_clk16x = DFFEAS(C1_clk16x_lut_out, clk, VCC, , C1L54, , , , );


--C1L1 is txt:inst1|add~159
--operation mode is arithmetic

C1L1 = !C1_counter2[0];

--C1L2 is txt:inst1|add~159COUT
--operation mode is arithmetic

C1L2 = CARRY(C1_counter2[0]);


--C1L51 is txt:inst1|add~166
--operation mode is arithmetic

C1L51_carry_eqn = C1L41;
C1L51 = C1_counter2[7] $ (C1L51_carry_eqn);

--C1L61 is txt:inst1|add~166COUT
--operation mode is arithmetic

C1L61 = CARRY(!C1L41 # !C1_counter2[7]);


--C1L31 is txt:inst1|add~165
--operation mode is arithmetic

C1L31_carry_eqn = C1L21;
C1L31 = C1_counter2[6] $ (!C1L31_carry_eqn);

--C1L41 is txt:inst1|add~165COUT
--operation mode is arithmetic

C1L41 = CARRY(C1_counter2[6] & !C1L21);


--C1L11 is txt:inst1|add~164
--operation mode is arithmetic

C1L11_carry_eqn = C1L01;
C1L11 = C1_counter2[5] $ (C1L11_carry_eqn);

--C1L21 is txt:inst1|add~164COUT
--operation mode is arithmetic

C1L21 = CARRY(!C1L01 # !C1_counter2[5]);


--C1L71 is txt:inst1|add~167
--operation mode is normal

C1L71_carry_eqn = C1L61;
C1L71 = C1_counter2[8] $ (!C1L71_carry_eqn);


--C1L9 is txt:inst1|add~163
--operation mode is arithmetic

C1L9_carry_eqn = C1L8;
C1L9 = C1_counter2[4] $ (!C1L9_carry_eqn);