📄 rcvr.sim.vwf

📁 基于vhdl 的串行接口具有完整的程序
💻 VWF
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上一页 12
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 150000.0;
	}
}

TRANSITION_LIST("tbr[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 685.076;
		LEVEL 1 FOR 149314.924;
	}
}

TRANSITION_LIST("tbr[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 685.076;
		LEVEL 1 FOR 149314.924;
	}
}

TRANSITION_LIST("tbr[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 150000.0;
	}
}

TRANSITION_LIST("tsr[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 40232.691;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 8640.0;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 66567.309;
	}
}

TRANSITION_LIST("tsr[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 31592.691;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 8640.0;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 75207.309;
	}
}

TRANSITION_LIST("tsr[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 14312.691;
		LEVEL 1 FOR 25920.0;
		LEVEL 0 FOR 8640.0;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 83847.309;
	}
}

TRANSITION_LIST("tsr[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 14312.691;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 8640.0;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 92487.309;
	}
}

TRANSITION_LIST("tsr[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 31592.691;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 101127.309;
	}
}

TRANSITION_LIST("tsr[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 14312.691;
		LEVEL 1 FOR 25920.0;
		LEVEL 0 FOR 109767.309;
	}
}

TRANSITION_LIST("tsr[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 14312.691;
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 118407.309;
	}
}

TRANSITION_LIST("tsr[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 150000.0;
	}
}

TRANSITION_LIST("lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5672.691;
		NODE
		{
			REPEAT = 6;
			LEVEL 1 FOR 8640.0;
			LEVEL 0 FOR 8640.0;
		}
		LEVEL 1 FOR 543.818;
		LEVEL 0 FOR 40103.491;
	}
}

TRANSITION_LIST("lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 14312.691;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 17280.0;
			LEVEL 0 FOR 17280.0;
		}
		LEVEL 1 FOR 17280.0;
		LEVEL 0 FOR 49287.309;
	}
}

TRANSITION_LIST("lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 31592.691;
		LEVEL 1 FOR 34560.0;
		LEVEL 0 FOR 34560.0;
		LEVEL 1 FOR 9183.818;
		LEVEL 0 FOR 40103.491;
	}
}

TRANSITION_LIST("lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 66152.691;
		LEVEL 1 FOR 43743.818;
		LEVEL 0 FOR 40103.491;
	}
}

TRANSITION_LIST("clk1x")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5666.722;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 4320.0;
			LEVEL 0 FOR 4320.0;
		}
		LEVEL 1 FOR 40653.278;
	}
}

DISPLAY_LINE
{
	CHANNEL = "wrn";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "din";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
	CHILDREN = 3, 4, 5, 6, 7, 8, 9, 10;
}

DISPLAY_LINE
{
	CHANNEL = "din[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "din[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "din[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "din[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "din[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "din[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "din[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "din[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 2;
}

DISPLAY_LINE
{
	CHANNEL = "sdo";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 11;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk1x";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 12;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk16x";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 13;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "tbr";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 14;
	TREE_LEVEL = 0;
	CHILDREN = 15, 16, 17, 18, 19, 20, 21, 22;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tbr[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "tsr";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 23;
	TREE_LEVEL = 0;
	CHILDREN = 24, 25, 26, 27, 28, 29, 30, 31;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "tsr[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 32;
	TREE_LEVEL = 0;
	CHILDREN = 33, 34, 35, 36;
}

DISPLAY_LINE
{
	CHANNEL = "lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 33;
	TREE_LEVEL = 1;
	PARENT = 32;
}

DISPLAY_LINE
{
	CHANNEL = "lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 34;
	TREE_LEVEL = 1;
	PARENT = 32;
}

DISPLAY_LINE
{
	CHANNEL = "lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 35;
	TREE_LEVEL = 1;
	PARENT = 32;
}

DISPLAY_LINE
{
	CHANNEL = "lpm_counter:no_bits_sent_rtl_0|cntr_p47:auto_generated|safe_q[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 36;
	TREE_LEVEL = 1;
	PARENT = 32;
}

TIME_BAR
{
	TIME = 11850;
	MASTER = TRUE;
}
;
上一页 12
💿 文件大小 260 K
👤 上传用户 uimeet
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#vhdl #串行接口 #程序
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