rcvr.map.qmsg

基于vhdl 的串行接口 具有完整的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 26 10:27:58 2005 " "Info: Processing started: Mon Sep 26 10:27:58 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off rcvr -c rcvr " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off rcvr -c rcvr" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rcvr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rcvr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rcvr-v1 " "Info: Found design unit 1: rcvr-v1" {  } { { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rcvr " "Info: Found entity 1: rcvr" {  } { { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file txt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 txt-v1 " "Info: Found design unit 1: txt-v1" {  } { { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 txt " "Info: Found entity 1: txt" {  } { { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 uart " "Info: Found entity 1: uart" {  } { { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "txt:inst1\|counter1\[0\] rcvr:inst\|counter1\[0\] " "Info: Duplicate register \"txt:inst1\|counter1\[0\]\" merged to single register \"rcvr:inst\|counter1\[0\]\"" {  } { { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "txt:inst1\|no_bits_sent\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"txt:inst1\|no_bits_sent\[0\]~8\"" {  } { { "txt.vhd" "no_bits_sent\[0\]~8" { Text "F:/quartus/串口/receiver/txt.vhd" 103 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "rcvr:inst\|no_bits_rcvd\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"rcvr:inst\|no_bits_rcvd\[0\]~8\"" {  } { { "rcvr.vhd" "no_bits_rcvd\[0\]~8" { Text "F:/quartus/串口/receiver/rcvr.vhd" 89 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_p47.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_p47.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_p47 " "Info: Found entity 1: cntr_p47" {  } { { "db/cntr_p47.tdf" "" { Text "F:/quartus/串口/receiver/db/cntr_p47.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "146 " "Info: Implemented 146 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "126 " "Info: Implemented 126 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 26 10:28:02 2005 " "Info: Processing ended: Mon Sep 26 10:28:02 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}