rcvr.tan.qmsg

基于vhdl 的串行接口 具有完整的程序

{ "Info" "ITDB_TSU_RESULT" "txt:inst1\|tbr\[5\] din\[5\] wrn -1.012 ns register " "Info: tsu for register \"txt:inst1\|tbr\[5\]\" (data pin = \"din\[5\]\", clock pin = \"wrn\") is -1.012 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.681 ns + Longest pin register " "Info: + Longest pin to register delay is 6.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns din\[5\] 1 PIN PIN_40 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 1; PIN Node = 'din\[5\]'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { din[5] } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 208 0 168 224 "din\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.946 ns) + CELL(0.603 ns) 6.681 ns txt:inst1\|tbr\[5\] 2 REG LC_X2_Y6_N1 1 " "Info: 2: + IC(4.946 ns) + CELL(0.603 ns) = 6.681 ns; Loc. = LC_X2_Y6_N1; Fanout = 1; REG Node = 'txt:inst1\|tbr\[5\]'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "5.549 ns" { din[5] txt:inst1|tbr[5] } "NODE_NAME" } "" } } { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.735 ns 25.97 % " "Info: Total cell delay = 1.735 ns ( 25.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.946 ns 74.03 % " "Info: Total interconnect delay = 4.946 ns ( 74.03 % )" {  } {  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "6.681 ns" { din[5] txt:inst1|tbr[5] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "6.681 ns" { din[5] din[5]~combout txt:inst1|tbr[5] } { 0.000ns 0.000ns 4.946ns } { 0.000ns 1.132ns 0.603ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.180 ns + " "Info: + Micro setup delay of destination is 0.180 ns" {  } { { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrn destination 7.873 ns - Shortest register " "Info: - Shortest clock path from clock \"wrn\" to destination register is 7.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns wrn 1 CLK PIN_37 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_37; Fanout = 9; CLK Node = 'wrn'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { wrn } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 192 0 168 208 "wrn" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.804 ns) + CELL(0.937 ns) 7.873 ns txt:inst1\|tbr\[5\] 2 REG LC_X2_Y6_N1 1 " "Info: 2: + IC(5.804 ns) + CELL(0.937 ns) = 7.873 ns; Loc. = LC_X2_Y6_N1; Fanout = 1; REG Node = 'txt:inst1\|tbr\[5\]'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "6.741 ns" { wrn txt:inst1|tbr[5] } "NODE_NAME" } "" } } { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.069 ns 26.28 % " "Info: Total cell delay = 2.069 ns ( 26.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.804 ns 73.72 % " "Info: Total interconnect delay = 5.804 ns ( 73.72 % )" {  } {  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "7.873 ns" { wrn txt:inst1|tbr[5] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.873 ns" { wrn wrn~combout txt:inst1|tbr[5] } { 0.000ns 0.000ns 5.804ns } { 0.000ns 1.132ns 0.937ns } } }  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "6.681 ns" { din[5] txt:inst1|tbr[5] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "6.681 ns" { din[5] din[5]~combout txt:inst1|tbr[5] } { 0.000ns 0.000ns 4.946ns } { 0.000ns 1.132ns 0.603ns } } } { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "7.873 ns" { wrn txt:inst1|tbr[5] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.873 ns" { wrn wrn~combout txt:inst1|tbr[5] } { 0.000ns 0.000ns 5.804ns } { 0.000ns 1.132ns 0.937ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[0\] rcvr:inst\|rbr\[0\] 13.891 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[0\]\" through register \"rcvr:inst\|rbr\[0\]\" is 13.891 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.133 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 31 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 31; CLK Node = 'clk'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { clk } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns rcvr:inst\|clk1x 2 REG LC_X10_Y5_N6 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X10_Y5_N6; Fanout = 21; REG Node = 'rcvr:inst\|clk1x'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "3.059 ns" { clk rcvr:inst|clk1x } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.974 ns) + CELL(0.937 ns) 9.133 ns rcvr:inst\|rbr\[0\] 3 REG LC_X9_Y10_N5 1 " "Info: 3: + IC(3.974 ns) + CELL(0.937 ns) = 9.133 ns; Loc. = LC_X9_Y10_N5; Fanout = 1; REG Node = 'rcvr:inst\|rbr\[0\]'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.911 ns" { rcvr:inst|clk1x rcvr:inst|rbr[0] } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 37.46 % " "Info: Total cell delay = 3.421 ns ( 37.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.712 ns 62.54 % " "Info: Total interconnect delay = 5.712 ns ( 62.54 % )" {  } {  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|rbr[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|rbr[0] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.384 ns + " "Info: + Micro clock to output delay of source is 0.384 ns" {  } { { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.374 ns + Longest register pin " "Info: + Longest register to pin delay is 4.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rcvr:inst\|rbr\[0\] 1 REG LC_X9_Y10_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y10_N5; Fanout = 1; REG Node = 'rcvr:inst\|rbr\[0\]'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { rcvr:inst|rbr[0] } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.052 ns) + CELL(2.322 ns) 4.374 ns dout\[0\] 2 PIN PIN_131 0 " "Info: 2: + IC(2.052 ns) + CELL(2.322 ns) = 4.374 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'dout\[0\]'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.374 ns" { rcvr:inst|rbr[0] dout[0] } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 80 392 568 96 "dout\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 53.09 % " "Info: Total cell delay = 2.322 ns ( 53.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.052 ns 46.91 % " "Info: Total interconnect delay = 2.052 ns ( 46.91 % )" {  } {  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.374 ns" { rcvr:inst|rbr[0] dout[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "4.374 ns" { rcvr:inst|rbr[0] dout[0] } { 0.000ns 2.052ns } { 0.000ns 2.322ns } } }  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|rbr[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|rbr[0] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.374 ns" { rcvr:inst|rbr[0] dout[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "4.374 ns" { rcvr:inst|rbr[0] dout[0] } { 0.000ns 2.052ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "txt:inst1\|wrn1 wrn clk 2.454 ns register " "Info: th for register \"txt:inst1\|wrn1\" (data pin = \"wrn\", clock pin = \"clk\") is 2.454 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.477 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.477 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 31 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 31; CLK Node = 'clk'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { clk } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns txt:inst1\|clk16x 2 REG LC_X3_Y8_N2 4 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X3_Y8_N2; Fanout = 4; REG Node = 'txt:inst1\|clk16x'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "3.059 ns" { clk txt:inst1|clk16x } "NODE_NAME" } "" } } { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.318 ns) + CELL(0.937 ns) 6.477 ns txt:inst1\|wrn1 3 REG LC_X2_Y8_N4 2 " "Info: 3: + IC(1.318 ns) + CELL(0.937 ns) = 6.477 ns; Loc. = LC_X2_Y8_N4; Fanout = 2; REG Node = 'txt:inst1\|wrn1'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "2.255 ns" { txt:inst1|clk16x txt:inst1|wrn1 } "NODE_NAME" } "" } } { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 52.82 % " "Info: Total cell delay = 3.421 ns ( 52.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.056 ns 47.18 % " "Info: Total interconnect delay = 3.056 ns ( 47.18 % )" {  } {  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "6.477 ns" { clk txt:inst1|clk16x txt:inst1|wrn1 } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "6.477 ns" { clk clk~combout txt:inst1|clk16x txt:inst1|wrn1 } { 0.000ns 0.000ns 1.738ns 1.318ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.225 ns + " "Info: + Micro hold delay of destination is 0.225 ns" {  } { { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.248 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.248 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns wrn 1 CLK PIN_37 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_37; Fanout = 9; CLK Node = 'wrn'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { wrn } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 192 0 168 208 "wrn" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.830 ns) + CELL(0.286 ns) 4.248 ns txt:inst1\|wrn1 2 REG LC_X2_Y8_N4 2 " "Info: 2: + IC(2.830 ns) + CELL(0.286 ns) = 4.248 ns; Loc. = LC_X2_Y8_N4; Fanout = 2; REG Node = 'txt:inst1\|wrn1'" {  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "3.116 ns" { wrn txt:inst1|wrn1 } "NODE_NAME" } "" } } { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.418 ns 33.38 % " "Info: Total cell delay = 1.418 ns ( 33.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.830 ns 66.62 % " "Info: Total interconnect delay = 2.830 ns ( 66.62 % )" {  } {  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.248 ns" { wrn txt:inst1|wrn1 } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "4.248 ns" { wrn wrn~combout txt:inst1|wrn1 } { 0.000ns 0.000ns 2.830ns } { 0.000ns 1.132ns 0.286ns } } }  } 0}  } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "6.477 ns" { clk txt:inst1|clk16x txt:inst1|wrn1 } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "6.477 ns" { clk clk~combout txt:inst1|clk16x txt:inst1|wrn1 } { 0.000ns 0.000ns 1.738ns 1.318ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.248 ns" { wrn txt:inst1|wrn1 } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "4.248 ns" { wrn wrn~combout txt:inst1|wrn1 } { 0.000ns 0.000ns 2.830ns } { 0.000ns 1.132ns 0.286ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 26 10:28:16 2005 " "Info: Processing ended: Mon Sep 26 10:28:16 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}