📄 rcvr.tan.qmsg
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wrn " "Info: Assuming node \"wrn\" is an undefined clock" { } { { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 192 0 168 208 "wrn" "" } } } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "wrn" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "rcvr:inst\|clk16x " "Info: Detected ripple clock \"rcvr:inst\|clk16x\" as buffer" { } { { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 27 -1 0 } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "rcvr:inst\|clk16x" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "txt:inst1\|clk16x " "Info: Detected ripple clock \"txt:inst1\|clk16x\" as buffer" { } { { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 30 -1 0 } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "txt:inst1\|clk16x" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "rcvr:inst\|clk1x " "Info: Detected ripple clock \"rcvr:inst\|clk1x\" as buffer" { } { { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 40 -1 0 } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "rcvr:inst\|clk1x" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "txt:inst1\|clk1x " "Info: Detected ripple clock \"txt:inst1\|clk1x\" as buffer" { } { { "txt.vhd" "" { Text "F:/quartus/串口/receiver/txt.vhd" 42 -1 0 } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "txt:inst1\|clk1x" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register rcvr:inst\|lpm_counter:no_bits_rcvd_rtl_1\|cntr_p47:auto_generated\|safe_q\[3\] register rcvr:inst\|rbr\[2\] 83.26 MHz 12.01 ns Internal " "Info: Clock \"clk\" has Internal fmax of 83.26 MHz between source register \"rcvr:inst\|lpm_counter:no_bits_rcvd_rtl_1\|cntr_p47:auto_generated\|safe_q\[3\]\" and destination register \"rcvr:inst\|rbr\[2\]\" (period= 12.01 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.441 ns + Longest register register " "Info: + Longest register to register delay is 5.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rcvr:inst\|lpm_counter:no_bits_rcvd_rtl_1\|cntr_p47:auto_generated\|safe_q\[3\] 1 REG LC_X10_Y10_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N4; Fanout = 4; REG Node = 'rcvr:inst\|lpm_counter:no_bits_rcvd_rtl_1\|cntr_p47:auto_generated\|safe_q\[3\]'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_p47.tdf" "" { Text "F:/quartus/串口/receiver/db/cntr_p47.tdf" 76 8 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.114 ns) + CELL(0.932 ns) 3.046 ns rcvr:inst\|rbr\[7\]~47 2 COMB LC_X9_Y10_N9 8 " "Info: 2: + IC(2.114 ns) + CELL(0.932 ns) = 3.046 ns; Loc. = LC_X9_Y10_N9; Fanout = 8; COMB Node = 'rcvr:inst\|rbr\[7\]~47'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "3.046 ns" { rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] rcvr:inst|rbr[7]~47 } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.127 ns) + CELL(1.268 ns) 5.441 ns rcvr:inst\|rbr\[2\] 3 REG LC_X8_Y10_N3 1 " "Info: 3: + IC(1.127 ns) + CELL(1.268 ns) = 5.441 ns; Loc. = LC_X8_Y10_N3; Fanout = 1; REG Node = 'rcvr:inst\|rbr\[2\]'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "2.395 ns" { rcvr:inst|rbr[7]~47 rcvr:inst|rbr[2] } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 40.43 % " "Info: Total cell delay = 2.200 ns ( 40.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.241 ns 59.57 % " "Info: Total interconnect delay = 3.241 ns ( 59.57 % )" { } { } 0} } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "5.441 ns" { rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] rcvr:inst|rbr[7]~47 rcvr:inst|rbr[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "5.441 ns" { rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] rcvr:inst|rbr[7]~47 rcvr:inst|rbr[2] } { 0.000ns 2.114ns 1.127ns } { 0.000ns 0.932ns 1.268ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.133 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 9.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 31 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 31; CLK Node = 'clk'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { clk } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns rcvr:inst\|clk1x 2 REG LC_X10_Y5_N6 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X10_Y5_N6; Fanout = 21; REG Node = 'rcvr:inst\|clk1x'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "3.059 ns" { clk rcvr:inst|clk1x } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.974 ns) + CELL(0.937 ns) 9.133 ns rcvr:inst\|rbr\[2\] 3 REG LC_X8_Y10_N3 1 " "Info: 3: + IC(3.974 ns) + CELL(0.937 ns) = 9.133 ns; Loc. = LC_X8_Y10_N3; Fanout = 1; REG Node = 'rcvr:inst\|rbr\[2\]'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.911 ns" { rcvr:inst|clk1x rcvr:inst|rbr[2] } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 37.46 % " "Info: Total cell delay = 3.421 ns ( 37.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.712 ns 62.54 % " "Info: Total interconnect delay = 5.712 ns ( 62.54 % )" { } { } 0} } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|rbr[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|rbr[2] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.133 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 31 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 31; CLK Node = 'clk'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "" { clk } "NODE_NAME" } "" } } { "uart.bdf" "" { Schematic "F:/quartus/串口/receiver/uart.bdf" { { 80 0 168 96 "clk" "" } { 168 168 208 184 "clk" "" } { 72 168 208 88 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns rcvr:inst\|clk1x 2 REG LC_X10_Y5_N6 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X10_Y5_N6; Fanout = 21; REG Node = 'rcvr:inst\|clk1x'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "3.059 ns" { clk rcvr:inst|clk1x } "NODE_NAME" } "" } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.974 ns) + CELL(0.937 ns) 9.133 ns rcvr:inst\|lpm_counter:no_bits_rcvd_rtl_1\|cntr_p47:auto_generated\|safe_q\[3\] 3 REG LC_X10_Y10_N4 4 " "Info: 3: + IC(3.974 ns) + CELL(0.937 ns) = 9.133 ns; Loc. = LC_X10_Y10_N4; Fanout = 4; REG Node = 'rcvr:inst\|lpm_counter:no_bits_rcvd_rtl_1\|cntr_p47:auto_generated\|safe_q\[3\]'" { } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "4.911 ns" { rcvr:inst|clk1x rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_p47.tdf" "" { Text "F:/quartus/串口/receiver/db/cntr_p47.tdf" 76 8 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 37.46 % " "Info: Total cell delay = 3.421 ns ( 37.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.712 ns 62.54 % " "Info: Total interconnect delay = 5.712 ns ( 62.54 % )" { } { } 0} } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } } 0} } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|rbr[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|rbr[2] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.384 ns + " "Info: + Micro clock to output delay of source is 0.384 ns" { } { { "db/cntr_p47.tdf" "" { Text "F:/quartus/串口/receiver/db/cntr_p47.tdf" 76 8 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.180 ns + " "Info: + Micro setup delay of destination is 0.180 ns" { } { { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "db/cntr_p47.tdf" "" { Text "F:/quartus/串口/receiver/db/cntr_p47.tdf" 76 8 0 } } { "rcvr.vhd" "" { Text "F:/quartus/串口/receiver/rcvr.vhd" 75 -1 0 } } } 0} } { { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "5.441 ns" { rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] rcvr:inst|rbr[7]~47 rcvr:inst|rbr[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "5.441 ns" { rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] rcvr:inst|rbr[7]~47 rcvr:inst|rbr[2] } { 0.000ns 2.114ns 1.127ns } { 0.000ns 0.932ns 1.268ns } } } { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|rbr[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|rbr[2] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" "" { Report "F:/quartus/串口/receiver/db/rcvr_cmp.qrpt" Compiler "rcvr" "UNKNOWN" "V1" "F:/quartus/串口/receiver/db/rcvr.quartus_db" { Floorplan "F:/quartus/串口/receiver/" "" "9.133 ns" { clk rcvr:inst|clk1x rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "9.133 ns" { clk clk~combout rcvr:inst|clk1x rcvr:inst|lpm_counter:no_bits_rcvd_rtl_1|cntr_p47:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.738ns 3.974ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "wrn " "Info: No valid register-to-register data paths exist for clock \"wrn\"" { } { } 0}
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