rcvr.fit.rpt

基于vhdl 的串行接口 具有完整的程序

; 8                                          ; 2                            ;
; 9                                          ; 2                            ;
; 10                                         ; 6                            ;
+--------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 1.50) ; Number of LABs  (Total = 22) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 2                            ;
; 1 Clock                            ; 19                           ;
; 1 Clock enable                     ; 10                           ;
; 2 Clocks                           ; 2                            ;
+------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Signals Sourced                                                        ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 5.73) ; Number of LABs  (Total = 22) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 9                            ;
; 2                                           ; 1                            ;
; 3                                           ; 0                            ;
; 4                                           ; 1                            ;
; 5                                           ; 0                            ;
; 6                                           ; 0                            ;
; 7                                           ; 1                            ;
; 8                                           ; 0                            ;
; 9                                           ; 1                            ;
; 10                                          ; 5                            ;
; 11                                          ; 3                            ;
; 12                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 3.73) ; Number of LABs  (Total = 22) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 11                           ;
; 2                                               ; 3                            ;
; 3                                               ; 1                            ;
; 4                                               ; 0                            ;
; 5                                               ; 0                            ;
; 6                                               ; 1                            ;
; 7                                               ; 0                            ;
; 8                                               ; 0                            ;
; 9                                               ; 4                            ;
; 10                                              ; 2                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 5.09) ; Number of LABs  (Total = 22) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 8                            ;
; 3                                           ; 5                            ;
; 4                                           ; 2                            ;
; 5                                           ; 0                            ;
; 6                                           ; 0                            ;
; 7                                           ; 1                            ;
; 8                                           ; 0                            ;
; 9                                           ; 0                            ;
; 10                                          ; 2                            ;
; 11                                          ; 2                            ;
; 12                                          ; 2                            ;
+---------------------------------------------+------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Sep 26 10:28:05 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off rcvr -c rcvr
Info: Selected device EPM1270T144C5ES for design "rcvr"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM1270T144C5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "rcvr:inst|clk1x" to use Global clock
    Info: Destination "rcvr:inst|clk1x" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "txt:inst1|clk1x" to use Global clock
    Info: Destination "txt:inst1|clk1x" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "wrn" to use Global clock
    Info: Destination "txt:inst1|wrn1" may be non-global or may not use global clock
Info: Pin "wrn" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 4.057 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y10; Fanout = 1; REG Node = 'rcvr:inst|rbr[7]'
    Info: 2: + IC(1.735 ns) + CELL(2.322 ns) = 4.057 ns; Loc. = PIN_122; Fanout = 0; PIN Node = 'dout[7]'
    Info: Total cell delay = 2.322 ns ( 57.23 % )
    Info: Total interconnect delay = 1.735 ns ( 42.77 % )
Info: Estimated interconnect usage is 2% of the available device resources
Info: Fitter placement operations ending: elapsed time = 1 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Sep 26 10:28:09 2005
    Info: Elapsed time: 00:00:05