_synthesis.nlf

来自「倍频详解」· NLF 代码 · 共 20 行

NLF
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Release 9.1i - netgen J.30Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.Command Line: netgen -intstyle ise -ar Structure -tm dll_4 -w -dir
netgen/synthesis -ofmt vhdl -sim dll_4.ngc _synthesis.vhd  Reading design 'dll_4.ngc' ...Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing VHDL netlist
'D:\program\ISE\ISE+work\13\dll_4\netgen\synthesis\_synthesis.vhd' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM library for correct
   compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 56400 kilobytes

_synthesis.nlf - 源码说明

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