_synthesis.vhd

倍频详解

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: J.30
--  \   \         Application: netgen
--  /   /         Filename: _synthesis.vhd
-- /___/   /\     Timestamp: Thu Dec 06 16:27:26 2007
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -ar Structure -tm dll_4 -w -dir netgen/synthesis -ofmt vhdl -sim dll_4.ngc _synthesis.vhd 
-- Device	: xc2s15-6-tq144
-- Input file	: dll_4.ngc
-- Output file	: D:\program\ISE\ISE+work\13\dll_4\netgen\synthesis\_synthesis.vhd
-- # of Entities	: 1
-- Design Name	: dll_4
-- Xilinx	: D:\Program Files\Xilinx91i
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity dll_4 is
  port (
    clk : in STD_LOGIC := 'X'; 
    clkout : out STD_LOGIC 
  );
end dll_4;

architecture Structure of dll_4 is
  signal clkout_OBUF_0 : STD_LOGIC; 
  signal LOCKED2X_delay : STD_LOGIC; 
  signal clk2_fb : STD_LOGIC; 
  signal clk_1 : STD_LOGIC; 
  signal CLK2X : STD_LOGIC; 
  signal clk1_fb : STD_LOGIC; 
  signal LOCKED2X : STD_LOGIC; 
  signal CLK2_RST : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal NLW_u1_CLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_u1_CLK90_UNCONNECTED : STD_LOGIC; 
  signal NLW_u1_CLK180_UNCONNECTED : STD_LOGIC; 
  signal NLW_u1_CLK270_UNCONNECTED : STD_LOGIC; 
  signal NLW_u1_CLKDV_UNCONNECTED : STD_LOGIC; 
  signal NLW_U5_CLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_U5_CLK90_UNCONNECTED : STD_LOGIC; 
  signal NLW_U5_CLK180_UNCONNECTED : STD_LOGIC; 
  signal NLW_U5_CLK270_UNCONNECTED : STD_LOGIC; 
  signal NLW_U5_CLKDV_UNCONNECTED : STD_LOGIC; 
  signal NLW_U5_LOCKED_UNCONNECTED : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  u0 : IBUFG
    port map (
      I => clk,
      O => clk_1
    );
  u1 : CLKDLL
    generic map(
      CLKDV_DIVIDE => 2.0000,
      DUTY_CYCLE_CORRECTION => TRUE,
      FACTORY_JF => X"C080",
      STARTUP_WAIT => FALSE
    )
    port map (
      CLKIN => clk_1,
      CLKFB => clk1_fb,
      RST => N0,
      CLK0 => NLW_u1_CLK0_UNCONNECTED,
      CLK90 => NLW_u1_CLK90_UNCONNECTED,
      CLK180 => NLW_u1_CLK180_UNCONNECTED,
      CLK270 => NLW_u1_CLK270_UNCONNECTED,
      CLK2X => CLK2X,
      CLKDV => NLW_u1_CLKDV_UNCONNECTED,
      LOCKED => LOCKED2X
    );
  u2 : BUFG
    port map (
      I => CLK2X,
      O => clk1_fb
    );
  u3 : SRL16
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1,
      CLK => clk1_fb,
      D => LOCKED2X,
      Q => LOCKED2X_delay
    );
  U4 : INV
    port map (
      I => LOCKED2X_delay,
      O => CLK2_RST
    );
  U5 : CLKDLL
    generic map(
      CLKDV_DIVIDE => 2.0000,
      DUTY_CYCLE_CORRECTION => TRUE,
      FACTORY_JF => X"C080",
      STARTUP_WAIT => FALSE
    )
    port map (
      CLKIN => clk1_fb,
      CLKFB => clk2_fb,
      RST => CLK2_RST,
      CLK0 => NLW_U5_CLK0_UNCONNECTED,
      CLK90 => NLW_U5_CLK90_UNCONNECTED,
      CLK180 => NLW_U5_CLK180_UNCONNECTED,
      CLK270 => NLW_U5_CLK270_UNCONNECTED,
      CLK2X => clkout_OBUF_0,
      CLKDV => NLW_U5_CLKDV_UNCONNECTED,
      LOCKED => NLW_U5_LOCKED_UNCONNECTED
    );
  u6 : BUFG
    port map (
      I => clkout_OBUF_0,
      O => clk2_fb
    );
  clkout_OBUF : OBUF
    port map (
      I => clkout_OBUF_0,
      O => clkout
    );

end Structure;